clash-prelude: CAES Language for Synchronous Hardware - Prelude library

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CλaSH (pronounced ‘clash’) is a functional hardware description language that borrows both its syntax and semantics from the functional programming language Haskell. The CλaSH compiler transforms these high-level descriptions to low-level synthesizable VHDL, Verilog, or SystemVerilog.

Features of CλaSH:

Strongly typed, but with a very high degree of type inference, enabling both safe and fast prototyping using concise descriptions.
Interactive REPL: load your designs in an interpreter and easily test all your component without needing to setup a test bench.
Higher-order functions, with type inference, result in designs that are fully parametric by default.
Synchronous sequential circuit design based on streams of values, called Signals, lead to natural descriptions of feedback loops.
Support for multiple clock domains, with type safe clock domain crossing.

This package provides:

Prelude library containing datatypes and functions for circuit design

To use the library:

Import Clash.Prelude
Alternatively, if you want to explicitly route clock and reset ports, for more straightforward multi-clock designs, you can import the Clash.Explicit.Prelude module. Note that you should not import Clash.Prelude and Clash.Explicit.Prelude at the same time as they have overlapping definitions.

A preliminary version of a tutorial can be found in Clash.Tutorial, for a general overview of the library you should however check out Clash.Prelude. Some circuit examples can be found in Clash.Examples.

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Properties

Versions	0.2, 0.3, 0.4, 0.5, 0.5.0.1, 0.5.1, 0.6, 0.6.0.1, 0.7, 0.7.1, 0.7.2, 0.7.3, 0.7.4, 0.7.5, 0.8, 0.8.1, 0.9, 0.9.1, 0.9.2, 0.9.3, 0.10, 0.10.1, 0.10.2, 0.10.3, 0.10.4, 0.10.5, 0.10.6, 0.10.7, 0.10.8, 0.10.9, 0.10.10, 0.10.11, 0.10.13, 0.10.14, 0.11, 0.11.1, 0.11.2, 0.99, 0.99.1, 0.99.1, 0.99.2, 0.99.3, 1.0.0, 1.0.1, 1.2.0, 1.2.1, 1.2.2, 1.2.3, 1.2.4, 1.2.5, 1.4.0, 1.4.1, 1.4.2, 1.4.3, 1.4.4, 1.4.5, 1.4.6, 1.4.7, 1.6.0, 1.6.1, 1.6.2, 1.6.3, 1.6.4, 1.6.5, 1.6.6, 1.8.0, 1.8.1
Change log	CHANGELOG.md
Dependencies	array (>=0.5.1.0 && <0.6), base (>=4.8.0.0 && <5), bifunctors (>=5.4.0 && <6.0), constraints (>=0.8 && <1.0), data-binary-ieee754 (>=0.4.4 && <0.6), data-default (>=0.5.3 && <0.8), deepseq (>=1.4.1.0 && <1.5), ghc-prim (>=0.3.1.0 && <0.6), ghc-typelits-extra (>=0.2.5 && <0.3), ghc-typelits-knownnat (>=0.5 && <0.6), ghc-typelits-natnormalise (>=0.6 && <0.7), half (>=0.2.2.3 && <1.0), integer-gmp (>=0.5.1.0 && <1.1), lens (>=4.9 && <4.17), QuickCheck (>=2.7 && <2.12), reflection (>=2 && <2.2), singletons (>=1.0 && <3.0), template-haskell (>=2.12.0.0 && <2.14), transformers (>=0.4.2.0 && <0.6), vector (>=0.11 && <1.0) [details]
License	BSD-2-Clause
Copyright	Copyright © 2013-2016, University of Twente, 2016-2017, Myrtle Software Ltd, 2017 , QBayLogic, Google Inc.
Author	Christiaan Baaij
Maintainer	Christiaan Baaij <christiaan.baaij@gmail.com>
Category	Hardware
Home page	http://www.clash-lang.org/
Bug tracker	http://github.com/clash-lang/clash-prelude/issues
Source repo	head: git clone https://github.com/clash-lang/clash-prelude.git
Uploaded	by ChristiaanBaaij at 2018-05-12T09:00:23Z

Modules

[Index]

Clash

Flags

Manual Flags

Name	Description	Default
doctests	You can disable testing with doctests using `-f-doctests`.	Enabled
benchmarks	You can disable testing with benchmarks using `-f-benchmarks`.	Enabled

Use -f <flag> to enable a flag, or -f -<flag> to disable that flag. More info

Downloads

clash-prelude-0.99.1.tar.gz [browse] (Cabal source package)
Package description (as included in the package)

Maintainer's Corner

Package maintainers

ChristiaanBaaij, QBayLogic

For package maintainers and hackage trustees

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Readme for clash-prelude-0.99.1

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CλaSH - A functional hardware description language

WARNING Only works with GHC-8.2 or higher (http://www.haskell.org/ghc/download_ghc_8_4_2)!

Features of CλaSH:

Strongly typed, yet with a very high degree of type inference, enabling both safe and fast prototyping using concise descriptions.
Interactive REPL: load your designs in an interpreter and easily test all your component without needing to setup a test bench.
Higher-order functions, with type inference, result in designs that are fully parametric by default.
Synchronous sequential circuit design based on streams of values, called Signals, lead to natural descriptions of feedback loops.
Support for multiple clock domains, with type safe clock domain crossing.

Support

For updates and questions join the mailing list clash-language+subscribe@googlegroups.com or read the forum