clash-prelude-0.99.1: CAES Language for Synchronous Hardware - Prelude library

Copyright(C) 2015-2016 University of Twente
2016-2017 Myrtle Software Ltd
2017 Google Inc.
LicenseBSD2 (see the file LICENSE)
MaintainerChristiaan Baaij <christiaan.baaij@gmail.com>
Safe HaskellSafe
LanguageHaskell2010
Extensions
  • Cpp
  • MonoLocalBinds
  • ScopedTypeVariables
  • TypeFamilies
  • DataKinds
  • KindSignatures
  • TypeOperators
  • ExplicitNamespaces
  • ExplicitForAll
  • TypeApplications

Clash.Explicit.Synchronizer

Contents

Description

Synchronizer circuits for safe clock domain crossings

Synopsis

Bit-synchronizers

dualFlipFlopSynchronizer Source #

Arguments

:: Clock domain1 gated1

Clock to which the incoming data is synchronised

-> Clock domain2 gated2

Clock to which the outgoing data is synchronised

-> Reset domain2 synchronous

Reset for registers on the outgoing domain

-> a

Initial value of the two synchronisation registers

-> Signal domain1 a

Incoming data

-> Signal domain2 a

Outgoing, synchronised, data

Synchroniser based on two sequentially connected flip-flops.

  • NB: This synchroniser can be used for bit-synchronization.

  • NB: Although this synchroniser does reduce metastability, it does not guarantee the proper synchronisation of a whole word. For example, given that the output is sampled twice as fast as the input is running, and we have two samples in the input stream that look like:

    [0111,1000]

    But the circuit driving the input stream has a longer propagation delay on msb compared to the lsbs. What can happen is an output stream that looks like this:

    [0111,0111,0000,1000]

    Where the level-change of the msb was not captured, but the level change of the lsbs were.

    If you want to have safe word-synchronisation use asyncFIFOSynchronizer.

Word-synchronizers

asyncFIFOSynchronizer Source #

Arguments

:: 2 <= addrSize 
=> SNat addrSize

Size of the internally used addresses, the FIFO contains 2^addrSize elements.

-> Clock wdomain wgated

Clock to which the write port is synchronised

-> Clock rdomain rgated

Clock to which the read port is synchronised

-> Reset wdomain synchronous 
-> Reset rdomain synchronous 
-> Signal rdomain Bool

Read request

-> Signal wdomain (Maybe a)

Element to insert

-> (Signal rdomain a, Signal rdomain Bool, Signal wdomain Bool)

(Oldest element in the FIFO, empty flag, full flag)

Synchroniser implemented as a FIFO around an asynchronous RAM. Based on the design described in Clash.Tutorial, which is itself based on the design described in http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO1.pdf.

NB: This synchroniser can be used for word-synchronization.