clash-prelude: CAES Language for Synchronous Hardware - Prelude library

[ bsd2, hardware, library ] [ Propose Tags ]

CλaSH (pronounced ‘clash’) is a functional hardware description language that borrows both its syntax and semantics from the functional programming language Haskell. The CλaSH compiler transforms these high-level descriptions to low-level synthesizable VHDL, Verilog, or SystemVerilog.

Features of CλaSH:

  • Strongly typed (like VHDL), yet with a very high degree of type inference, enabling both safe and fast prototying using consise descriptions (like Verilog).

  • Interactive REPL: load your designs in an interpreter and easily test all your component without needing to setup a test bench.

  • Higher-order functions, with type inference, result in designs that are fully parametric by default.

  • Synchronous sequential circuit design based on streams of values, called Signals, lead to natural descriptions of feedback loops.

  • Support for multiple clock domains, with type safe clock domain crossing.

This package provides:

  • Prelude library containing datatypes and functions for circuit design

To use the library:

A preliminary version of a tutorial can be found in CLaSH.Tutorial, for a general overview of the library you should however check out CLaSH.Prelude. Some circuit examples can be found in CLaSH.Examples.


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Versions [RSS] 0.2, 0.3, 0.4, 0.5, 0.5.0.1, 0.5.1, 0.6, 0.6.0.1, 0.7, 0.7.1, 0.7.2, 0.7.3, 0.7.4, 0.7.5, 0.8, 0.8.1, 0.9, 0.9.1, 0.9.2, 0.9.3, 0.10, 0.10.1, 0.10.2, 0.10.3, 0.10.4, 0.10.5, 0.10.6, 0.10.7, 0.10.8, 0.10.9, 0.10.10, 0.10.11, 0.10.13, 0.10.14, 0.11, 0.11.1, 0.11.2, 0.99, 0.99.1, 0.99.2, 0.99.3, 1.0.0, 1.0.1, 1.2.0, 1.2.1, 1.2.2, 1.2.3, 1.2.4, 1.2.5, 1.4.0, 1.4.1, 1.4.2, 1.4.3, 1.4.4, 1.4.5, 1.4.6, 1.4.7, 1.6.0, 1.6.1, 1.6.2, 1.6.3, 1.6.4, 1.6.5, 1.6.6, 1.8.0, 1.8.1 (info)
Change log CHANGELOG.md
Dependencies array (>=0.5.1.0), base (>=4.8.0.0 && <5), data-default (>=0.5.3), ghc-prim (>=0.3.1.0), ghc-typelits-extra (>=0.1), ghc-typelits-natnormalise (>=0.3), integer-gmp (>=0.5.1.0), lens (>=4.9), QuickCheck (>=2.7 && <2.9), reflection (>=2), singletons (>=1.0 && <3.0), template-haskell (>=2.9.0.0), th-lift (>=0.5.6) [details]
License BSD-2-Clause
Copyright Copyright © 2013-2015 University of Twente
Author Christiaan Baaij
Maintainer Christiaan Baaij <christiaan.baaij@gmail.com>
Category Hardware
Home page http://www.clash-lang.org/
Bug tracker http://github.com/clash-lang/clash-prelude/issues
Source repo head: git clone https://github.com/clash-lang/clash-prelude.git
Uploaded by ChristiaanBaaij at 2015-10-24T09:30:57Z
Distributions Arch:1.8.0, LTSHaskell:1.8.1, Stackage:1.8.1
Reverse Dependencies 16 direct, 2 indirect [details]
Downloads 47765 total (228 in the last 30 days)
Rating 2.5 (votes: 3) [estimated by Bayesian average]
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Readme for clash-prelude-0.10.3

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CλaSH - A functional hardware description language

Build Status Hackage Hackage Dependencies

WARNING Only works with GHC-7.10.* (http://www.haskell.org/ghc/download_ghc_7_10_2)!

CλaSH (pronounced ‘clash’) is a functional hardware description language that borrows both its syntax and semantics from the functional programming language Haskell. The CλaSH compiler transforms these high-level descriptions to low-level synthesizable VHDL, Verilog, or SystemVerilog.

Features of CλaSH:

  • Strongly typed (like VHDL), yet with a very high degree of type inference, enabling both safe and fast prototying using consise descriptions (like Verilog).

  • Interactive REPL: load your designs in an interpreter and easily test all your component without needing to setup a test bench.

  • Higher-order functions, with type inference, result in designs that are fully parametric by default.

  • Synchronous sequential circuit design based on streams of values, called Signals, lead to natural descriptions of feedback loops.

  • Support for multiple clock domains, with type safe clock domain crossing.

Support

For updates and questions join the mailing list clash-language+subscribe@googlegroups.com or read the forum