Copyright	(C) 2015-2016 University of Twente 2017 Myrtle Software Ltd Google Inc.
License	BSD2 (see the file LICENSE)
Maintainer	Christiaan Baaij <christiaan.baaij@gmail.com>
Safe Haskell	Trustworthy
Language	Haskell2010
Extensions	Cpp MonoLocalBinds ScopedTypeVariables BangPatterns TypeFamilies DataKinds FlexibleContexts MagicHash KindSignatures TypeOperators ExplicitNamespaces ExplicitForAll TypeApplications

Clash.Explicit.RAM

Contents

Description

RAM primitives with a combinational read port.

Synopsis

asyncRam :: (Enum addr, HasCallStack) => Clock wdom wgated -> Clock rdom rgated -> SNat n -> Signal rdom addr -> Signal wdom (Maybe (addr, a)) -> Signal rdom a
asyncRamPow2 :: forall wdom rdom wgated rgated n a. (KnownNat n, HasCallStack) => Clock wdom wgated -> Clock rdom rgated -> Signal rdom (Unsigned n) -> Signal wdom (Maybe (Unsigned n, a)) -> Signal rdom a
asyncRam# :: HasCallStack => Clock wdom wgated -> Clock rdom rgated -> SNat n -> Signal rdom Int -> Signal wdom Bool -> Signal wdom Int -> Signal wdom a -> Signal rdom a

RAM synchronised to an arbitrary clock

Arguments

:: (Enum addr, HasCallStack)
=> Clock wdom wgated	`Clock` to which to synchronise the write port of the RAM
-> Clock rdom rgated	`Clock` to which the read address signal, `r`, is synchronised
-> SNat n	Size `n` of the RAM
-> Signal rdom addr	Read address `r`
-> Signal wdom (Maybe (addr, a))	(write address `w`, value to write)
-> Signal rdom a	Value of the `RAM` at address `r`

Create a RAM with space for n elements

Additional helpful information:

Arguments

:: (KnownNat n, HasCallStack)
=> Clock wdom wgated	`Clock` to which to synchronise the write port of the RAM
-> Clock rdom rgated	`Clock` to which the read address signal, `r`, is synchronised
-> Signal rdom (Unsigned n)	Read address `r`
-> Signal wdom (Maybe (Unsigned n, a))	(write address `w`, value to write)
-> Signal rdom a	Value of the `RAM` at address `r`

Create a RAM with space for 2^n elements

Additional helpful information:

Internal

Arguments

:: HasCallStack
=> Clock wdom wgated	`Clock` to which to synchronise the write port of the RAM
-> Clock rdom rgated	`Clock` to which the read address signal, `r`, is synchronised
-> SNat n	Size `n` of the RAM
-> Signal rdom Int	Read address `r`
-> Signal wdom Bool	Write enable
-> Signal wdom Int	Write address `w`
-> Signal wdom a	Value to write (at address `w`)
-> Signal rdom a	Value of the `RAM` at address `r`

RAM primitive