vkCmdSetEvent2 - Set an event object to signaled state

Description

When cmdSetEvent2 is submitted to a queue, it defines the first half of memory dependencies defined by pDependencyInfo, as well as an event signal operation which sets the event to the signaled state. A memory dependency is defined between the event signal operation and commands that occur earlier in submission order.

The first synchronization scope and access scope are defined by the union of all the memory dependencies defined by pDependencyInfo, and are applied to all operations that occur earlier in submission order. Queue family ownership transfers and image layout transitions defined by pDependencyInfo are also included in the first scopes.

The second synchronization scope includes only the event signal operation, and any queue family ownership transfers and image layout transitions defined by pDependencyInfo.

The second access scope includes only queue family ownership transfers and image layout transitions.

Future cmdWaitEvents2 commands rely on all values of each element in pDependencyInfo matching exactly with those used to signal the corresponding event. cmdWaitEvents must not be used to wait on the result of a signal operation defined by cmdSetEvent2.

Note

The extra information provided by cmdSetEvent2 compared to cmdSetEvent allows implementations to more efficiently schedule the operations required to satisfy the requested dependencies. With cmdSetEvent, the full dependency information is not known until cmdWaitEvents is recorded, forcing implementations to insert the required operations at that point and not before.

If event is already in the signaled state when cmdSetEvent2 is executed on the device, then cmdSetEvent2 has no effect, no event signal operation occurs, and no dependency is generated.

Valid Usage

• The synchronization2 feature must be enabled

• The dependencyFlags member of pDependencyInfo must be 0
• The srcStageMask member of any element of the pMemoryBarriers, pBufferMemoryBarriers, or pImageMemoryBarriers members of pDependencyInfo must not include PIPELINE_STAGE_2_HOST_BIT
• The dstStageMask member of any element of the pMemoryBarriers, pBufferMemoryBarriers, or pImageMemoryBarriers members of pDependencyInfo must not include PIPELINE_STAGE_2_HOST_BIT
• The current device mask of commandBuffer must include exactly one physical device
• The srcStageMask member of any element of the pMemoryBarriers, pBufferMemoryBarriers, or pImageMemoryBarriers members of pDependencyInfo must only include pipeline stages valid for the queue family that was used to create the command pool that commandBuffer was allocated from
• The dstStageMask member of any element of the pMemoryBarriers, pBufferMemoryBarriers, or pImageMemoryBarriers members of pDependencyInfo must only include pipeline stages valid for the queue family that was used to create the command pool that commandBuffer was allocated from

Valid Usage (Implicit)

• commandBuffer must be a valid CommandBuffer handle

• event must be a valid Event handle
• pDependencyInfo must be a valid pointer to a valid DependencyInfo structure
• commandBuffer must be in the recording state
• The CommandPool that commandBuffer was allocated from must support graphics, compute, decode, or encode operations
• This command must only be called outside of a render pass instance
• Both of commandBuffer, and event must have been created, allocated, or retrieved from the same Device

Host Synchronization

• Host access to commandBuffer must be externally synchronized

• Host access to the CommandPool that commandBuffer was allocated from must be externally synchronized

Command Properties

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See Also

VK_KHR_synchronization2, VK_VERSION_1_3, CommandBuffer, DependencyInfo, Event

vkCmdResetEvent2 - Reset an event object to non-signaled state

Description

When cmdResetEvent2 is submitted to a queue, it defines an execution dependency on commands that were submitted before it, and defines an event unsignal operation which resets the event to the unsignaled state.

The first synchronization scope includes all commands that occur earlier in submission order. The synchronization scope is limited to operations by stageMask or stages that are logically earlier than stageMask.

The second synchronization scope includes only the event unsignal operation.

If event is already in the unsignaled state when cmdResetEvent2 is executed on the device, then this command has no effect, no event unsignal operation occurs, and no execution dependency is generated.

Valid Usage

• If the geometryShader feature is not enabled, stageMask must not contain PIPELINE_STAGE_2_GEOMETRY_SHADER_BIT

• If the tessellationShader feature is not enabled, stageMask must not contain PIPELINE_STAGE_2_TESSELLATION_CONTROL_SHADER_BIT or PIPELINE_STAGE_2_TESSELLATION_EVALUATION_SHADER_BIT
• If the conditionalRendering feature is not enabled, stageMask must not contain PIPELINE_STAGE_2_CONDITIONAL_RENDERING_BIT_EXT
• If the fragmentDensityMap feature is not enabled, stageMask must not contain PIPELINE_STAGE_2_FRAGMENT_DENSITY_PROCESS_BIT_EXT
• If the transformFeedback feature is not enabled, stageMask must not contain PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT
• If the meshShader feature is not enabled, stageMask must not contain PIPELINE_STAGE_2_MESH_SHADER_BIT_EXT
• If the taskShader feature is not enabled, stageMask must not contain PIPELINE_STAGE_2_TASK_SHADER_BIT_EXT
• If neither the shadingRateImage or attachmentFragmentShadingRate are enabled, stageMask must not contain PIPELINE_STAGE_2_FRAGMENT_SHADING_RATE_ATTACHMENT_BIT_KHR
• If the subpassShading feature is not enabled, stageMask must not contain PIPELINE_STAGE_2_SUBPASS_SHADER_BIT_HUAWEI
• If the invocationMask feature is not enabled, stageMask must not contain PIPELINE_STAGE_2_INVOCATION_MASK_BIT_HUAWEI
• If neither the VK_NV_ray_tracing extension or rayTracingPipeline feature are enabled, stageMask must not contain PIPELINE_STAGE_2_RAY_TRACING_SHADER_BIT_KHR
• The synchronization2 feature must be enabled
• stageMask must not include PIPELINE_STAGE_2_HOST_BIT
• There must be an execution dependency between cmdResetEvent2 and the execution of any cmdWaitEvents that includes event in its pEvents parameter
• There must be an execution dependency between cmdResetEvent2 and the execution of any cmdWaitEvents2 that includes event in its pEvents parameter
• commandBuffer’s current device mask must include exactly one physical device

Valid Usage (Implicit)

• commandBuffer must be a valid CommandBuffer handle

• event must be a valid Event handle
• stageMask must be a valid combination of PipelineStageFlagBits2 values
• commandBuffer must be in the recording state
• The CommandPool that commandBuffer was allocated from must support graphics, compute, decode, or encode operations
• This command must only be called outside of a render pass instance
• Both of commandBuffer, and event must have been created, allocated, or retrieved from the same Device

Host Synchronization

• Host access to commandBuffer must be externally synchronized

• Host access to the CommandPool that commandBuffer was allocated from must be externally synchronized

Command Properties

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See Also

VK_KHR_synchronization2, VK_VERSION_1_3, CommandBuffer, Event, PipelineStageFlags2

vkCmdWaitEvents2 - Wait for one or more events

Description

When cmdWaitEvents2 is submitted to a queue, it inserts memory dependencies according to the elements of pDependencyInfos and each corresponding element of pEvents. cmdWaitEvents2 must not be used to wait on event signal operations occurring on other queues, or signal operations executed by cmdSetEvent.

The first synchronization scope and access scope of each memory dependency defined by any element i of pDependencyInfos are applied to operations that occurred earlier in submission order than the last event signal operation on element i of pEvents.

Signal operations for an event at index i are only included if:

• The event was signaled by a cmdSetEvent2 command that occurred earlier in submission order with a dependencyInfo parameter exactly equal to the element of pDependencyInfos at index i ; or
• The event was created without EVENT_CREATE_DEVICE_ONLY_BIT, and the first synchronization scope defined by the element of pDependencyInfos at index i only includes host operations (PIPELINE_STAGE_2_HOST_BIT).

The second synchronization scope and access scope of each memory dependency defined by any element i of pDependencyInfos are applied to operations that occurred later in submission order than cmdWaitEvents2.

Note

cmdWaitEvents2 is used with cmdSetEvent2 to define a memory dependency between two sets of action commands, roughly in the same way as pipeline barriers, but split into two commands such that work between the two may execute unhindered.

Note

Applications should be careful to avoid race conditions when using events. There is no direct ordering guarantee between cmdSetEvent2 and cmdResetEvent2, cmdResetEvent, or cmdSetEvent. Another execution dependency (e.g. a pipeline barrier or semaphore with PIPELINE_STAGE_2_ALL_COMMANDS_BIT) is needed to prevent such a race condition.

Valid Usage

• The synchronization2 feature must be enabled

• Members of pEvents must not have been signaled by cmdSetEvent
• For any element i of pEvents, if that event is signaled by cmdSetEvent2, that command’s dependencyInfo parameter must be exactly equal to the ith element of pDependencyInfos
• For any element i of pEvents, if that event is signaled by setEvent, barriers in the ith element of pDependencyInfos must include only host operations in their first synchronization scope
• For any element i of pEvents, if barriers in the ith element of pDependencyInfos include only host operations, the ith element of pEvents must be signaled before cmdWaitEvents2 is executed
• For any element i of pEvents, if barriers in the ith element of pDependencyInfos do not include host operations, the ith element of pEvents must be signaled by a corresponding cmdSetEvent2 that occurred earlier in submission order
• The srcStageMask member of any element of the pMemoryBarriers, pBufferMemoryBarriers, or pImageMemoryBarriers members of pDependencyInfos must either include only pipeline stages valid for the queue family that was used to create the command pool that commandBuffer was allocated from, or include only PIPELINE_STAGE_2_HOST_BIT
• The dstStageMask member of any element of the pMemoryBarriers, pBufferMemoryBarriers, or pImageMemoryBarriers members of pDependencyInfos must only include pipeline stages valid for the queue family that was used to create the command pool that commandBuffer was allocated from
• If cmdWaitEvents2 is being called inside a render pass instance, the srcStageMask member of any element of the pMemoryBarriers, pBufferMemoryBarriers, or pImageMemoryBarriers members of pDependencyInfos must not include PIPELINE_STAGE_2_HOST_BIT
• commandBuffer’s current device mask must include exactly one physical device

Valid Usage (Implicit)

• commandBuffer must be a valid CommandBuffer handle

• pEvents must be a valid pointer to an array of eventCount valid Event handles
• pDependencyInfos must be a valid pointer to an array of eventCount valid DependencyInfo structures
• commandBuffer must be in the recording state
• The CommandPool that commandBuffer was allocated from must support graphics, compute, decode, or encode operations
• eventCount must be greater than 0
• Both of commandBuffer, and the elements of pEvents must have been created, allocated, or retrieved from the same Device

Host Synchronization

• Host access to commandBuffer must be externally synchronized

• Host access to the CommandPool that commandBuffer was allocated from must be externally synchronized

Command Properties

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See Also

VK_KHR_synchronization2, VK_VERSION_1_3, CommandBuffer, DependencyInfo, Event

A variant of cmdWaitEvents2 which makes a *safe* FFI call

vkCmdPipelineBarrier2 - Insert a memory dependency

Description

When cmdPipelineBarrier2 is submitted to a queue, it defines memory dependencies between commands that were submitted to the same queue before it, and those submitted to the same queue after it.

The first synchronization scope and access scope of each memory dependency defined by pDependencyInfo are applied to operations that occurred earlier in submission order.

The second synchronization scope and access scope of each memory dependency defined by pDependencyInfo are applied to operations that occurred later in submission order.

If cmdPipelineBarrier2 is recorded within a render pass instance, the synchronization scopes are limited to operations within the same subpass , or must follow the restrictions for Tile Image Access Synchronization if the render pass instance was started with cmdBeginRendering .

Valid Usage

• If cmdPipelineBarrier2 is called within a render pass instance using a RenderPass object, the render pass must have been created with at least one subpass dependency that expresses a dependency from the current subpass to itself, does not include DEPENDENCY_BY_REGION_BIT if this command does not, does not include DEPENDENCY_VIEW_LOCAL_BIT if this command does not, and has synchronization scopes and access scopes that are all supersets of the scopes defined in this command

• If cmdPipelineBarrier2 is called within a render pass instance using a RenderPass object, it must not include any buffer memory barriers
• If cmdPipelineBarrier2 is called within a render pass instance using a RenderPass object, the image member of any image memory barrier included in this command must be an attachment used in the current subpass both as an input attachment, and as either a color, color resolve, or depth/stencil attachment
• If cmdPipelineBarrier2 is called within a render pass instance using a RenderPass object, and the image member of any image memory barrier is a color resolve attachment, the corresponding color attachment must be ATTACHMENT_UNUSED
• If cmdPipelineBarrier2 is called within a render pass instance using a RenderPass object, and the image member of any image memory barrier is a color resolve attachment, it must have been created with a non-zero ExternalFormatANDROID::externalFormat value
• If cmdPipelineBarrier2 is called within a render pass instance, the oldLayout and newLayout members of any image memory barrier included in this command must be equal
• If cmdPipelineBarrier2 is called within a render pass instance, the srcQueueFamilyIndex and dstQueueFamilyIndex members of any memory barrier included in this command must be equal
• If cmdPipelineBarrier2 is called within a render pass instance, and the source stage masks of any memory barriers include framebuffer-space stages, destination stage masks of all memory barriers must only include framebuffer-space stages
• If cmdPipelineBarrier2 is called within a render pass instance, and and the source stage masks of any memory barriers include framebuffer-space stages, then dependencyFlags must include DEPENDENCY_BY_REGION_BIT
• If cmdPipelineBarrier2 is called within a render pass instance, the source and destination stage masks of any memory barriers must only include graphics pipeline stages
• If cmdPipelineBarrier2 is called outside of a render pass instance, the dependency flags must not include DEPENDENCY_VIEW_LOCAL_BIT
• If cmdPipelineBarrier2 is called inside a render pass instance, and there is more than one view in the current subpass, dependency flags must include DEPENDENCY_VIEW_LOCAL_BIT
• If cmdPipelineBarrier2 is called within a render pass instance and none of the shaderTileImageColorReadAccess, shaderTileImageDepthReadAccess, shaderTileImageStencilReadAccess features are enabled, the render pass must not have been started with cmdBeginRendering
• If cmdPipelineBarrier2 is called within a render pass instance started with cmdBeginRendering, it must adhere to the restrictions in Explicit Render Pass Tile Image Access Synchronization
• The synchronization2 feature must be enabled
• The srcStageMask member of any element of the pMemoryBarriers, pBufferMemoryBarriers, or pImageMemoryBarriers members of pDependencyInfo must only include pipeline stages valid for the queue family that was used to create the command pool that commandBuffer was allocated from
• The dstStageMask member of any element of the pMemoryBarriers, pBufferMemoryBarriers, or pImageMemoryBarriers members of pDependencyInfo must only include pipeline stages valid for the queue family that was used to create the command pool that commandBuffer was allocated from

Valid Usage (Implicit)

• commandBuffer must be a valid CommandBuffer handle

• pDependencyInfo must be a valid pointer to a valid DependencyInfo structure
• commandBuffer must be in the recording state
• The CommandPool that commandBuffer was allocated from must support transfer, graphics, compute, decode, or encode operations

Host Synchronization

• Host access to commandBuffer must be externally synchronized

• Host access to the CommandPool that commandBuffer was allocated from must be externally synchronized

Command Properties

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See Also

VK_KHR_synchronization2, VK_VERSION_1_3, CommandBuffer, DependencyInfo

vkQueueSubmit2 - Submits command buffers to a queue

Description

queueSubmit2 is a queue submission command, with each batch defined by an element of pSubmits.

Semaphore operations submitted with queueSubmit2 have additional ordering constraints compared to other submission commands, with dependencies involving previous and subsequent queue operations. Information about these additional constraints can be found in the semaphore section of the synchronization chapter.

If any command buffer submitted to this queue is in the executable state, it is moved to the pending state. Once execution of all submissions of a command buffer complete, it moves from the pending state, back to the executable state. If a command buffer was recorded with the COMMAND_BUFFER_USAGE_ONE_TIME_SUBMIT_BIT flag, it instead moves back to the invalid state.

If queueSubmit2 fails, it may return ERROR_OUT_OF_HOST_MEMORY or ERROR_OUT_OF_DEVICE_MEMORY. If it does, the implementation must ensure that the state and contents of any resources or synchronization primitives referenced by the submitted command buffers and any semaphores referenced by pSubmits is unaffected by the call or its failure. If queueSubmit2 fails in such a way that the implementation is unable to make that guarantee, the implementation must return ERROR_DEVICE_LOST. See Lost Device.

Valid Usage

• If fence is not NULL_HANDLE, fence must be unsignaled

• If fence is not NULL_HANDLE, fence must not be associated with any other queue command that has not yet completed execution on that queue
• The synchronization2 feature must be enabled
• If a command recorded into the commandBuffer member of any element of the pCommandBufferInfos member of any element of pSubmits referenced an Event, that event must not be referenced by a command that has been submitted to another queue and is still in the pending state
• The semaphore member of any binary semaphore element of the pSignalSemaphoreInfos member of any element of pSubmits must be unsignaled when the semaphore signal operation it defines is executed on the device
• The stageMask member of any element of the pSignalSemaphoreInfos member of any element of pSubmits must only include pipeline stages that are supported by the queue family which queue belongs to
• The stageMask member of any element of the pWaitSemaphoreInfos member of any element of pSubmits must only include pipeline stages that are supported by the queue family which queue belongs to
• When a semaphore wait operation for a binary semaphore is executed, as defined by the semaphore member of any element of the pWaitSemaphoreInfos member of any element of pSubmits, there must be no other queues waiting on the same semaphore
• The semaphore member of any element of the pWaitSemaphoreInfos member of any element of pSubmits that was created with a SemaphoreTypeKHR of SEMAPHORE_TYPE_BINARY_KHR must reference a semaphore signal operation that has been submitted for execution and any semaphore signal operations on which it depends must have also been submitted for execution
• The commandBuffer member of any element of the pCommandBufferInfos member of any element of pSubmits must be in the pending or executable state
• If a command recorded into the commandBuffer member of any element of the pCommandBufferInfos member of any element of pSubmits was not recorded with the COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT, it must not be in the pending state
• Any secondary command buffers recorded into the commandBuffer member of any element of the pCommandBufferInfos member of any element of pSubmits must be in the pending or executable state
• If any secondary command buffers recorded into the commandBuffer member of any element of the pCommandBufferInfos member of any element of pSubmits was not recorded with the COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT, it must not be in the pending state
• The commandBuffer member of any element of the pCommandBufferInfos member of any element of pSubmits must have been allocated from a CommandPool that was created for the same queue family queue belongs to
• If a command recorded into the commandBuffer member of any element of the pCommandBufferInfos member of any element of pSubmits includes a Queue Family Transfer Acquire Operation, there must exist a previously submitted Queue Family Transfer Release Operation on a queue in the queue family identified by the acquire operation, with parameters matching the acquire operation as defined in the definition of such acquire operations, and which happens before the acquire operation
• If a command recorded into the commandBuffer member of any element of the pCommandBufferInfos member of any element of pSubmits was a cmdBeginQuery whose queryPool was created with a queryType of QUERY_TYPE_PERFORMANCE_QUERY_KHR, the profiling lock must have been held continuously on the Device that queue was retrieved from, throughout recording of those command buffers
• If queue was not created with DEVICE_QUEUE_CREATE_PROTECTED_BIT, the flags member of any element of pSubmits must not include SUBMIT_PROTECTED_BIT_KHR

Valid Usage (Implicit)

• queue must be a valid Queue handle

• If submitCount is not 0, pSubmits must be a valid pointer to an array of submitCount valid SubmitInfo2 structures
• If fence is not NULL_HANDLE, fence must be a valid Fence handle
• Both of fence, and queue that are valid handles of non-ignored parameters must have been created, allocated, or retrieved from the same Device

Host Synchronization

• Host access to queue must be externally synchronized

• Host access to fence must be externally synchronized

Command Properties

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Return Codes

Success

• SUCCESS

Failure

• ERROR_OUT_OF_HOST_MEMORY
• ERROR_OUT_OF_DEVICE_MEMORY
• ERROR_DEVICE_LOST

See Also

VK_KHR_synchronization2, VK_VERSION_1_3, Fence, Queue, SubmitInfo2

vkCmdWriteTimestamp2 - Write a device timestamp into a query object

Description

When cmdWriteTimestamp2 is submitted to a queue, it defines an execution dependency on commands that were submitted before it, and writes a timestamp to a query pool.

The first synchronization scope includes all commands that occur earlier in submission order. The synchronization scope is limited to operations on the pipeline stage specified by stage.

The second synchronization scope includes only the timestamp write operation.

Note

Implementations may write the timestamp at any stage that is logically later than stage.

Any timestamp write that happens-after another timestamp write in the same submission must not have a lower value unless its value overflows the maximum supported integer bit width of the query. If VK_EXT_calibrated_timestamps is enabled, this extends to timestamp writes across all submissions on the same logical device: any timestamp write that happens-after another must not have a lower value unless its value overflows the maximum supported integer bit width of the query. Timestamps written by this command must be in the TIME_DOMAIN_DEVICE_EXT time domain. If an overflow occurs, the timestamp value must wrap back to zero.

Note

Comparisons between timestamps should be done between timestamps where they are guaranteed to not decrease. For example, subtracting an older timestamp from a newer one to determine the execution time of a sequence of commands is only a reliable measurement if the two timestamp writes were performed in the same submission, or if the writes were performed on the same logical device and VK_EXT_calibrated_timestamps is enabled.

If cmdWriteTimestamp2 is called while executing a render pass instance that has multiview enabled, the timestamp uses N consecutive query indices in the query pool (starting at query) where N is the number of bits set in the view mask of the subpass the command is executed in. The resulting query values are determined by an implementation-dependent choice of one of the following behaviors:

• The first query is a timestamp value and (if more than one bit is set in the view mask) zero is written to the remaining queries. If two timestamps are written in the same subpass, the sum of the execution time of all views between those commands is the difference between the first query written by each command.
• All N queries are timestamp values. If two timestamps are written in the same subpass, the sum of the execution time of all views between those commands is the sum of the difference between corresponding queries written by each command. The difference between corresponding queries may be the execution time of a single view.

In either case, the application can sum the differences between all N queries to determine the total execution time.

Valid Usage

• If the geometryShader feature is not enabled, stage must not contain PIPELINE_STAGE_2_GEOMETRY_SHADER_BIT

• If the tessellationShader feature is not enabled, stage must not contain PIPELINE_STAGE_2_TESSELLATION_CONTROL_SHADER_BIT or PIPELINE_STAGE_2_TESSELLATION_EVALUATION_SHADER_BIT
• If the conditionalRendering feature is not enabled, stage must not contain PIPELINE_STAGE_2_CONDITIONAL_RENDERING_BIT_EXT
• If the fragmentDensityMap feature is not enabled, stage must not contain PIPELINE_STAGE_2_FRAGMENT_DENSITY_PROCESS_BIT_EXT
• If the transformFeedback feature is not enabled, stage must not contain PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT
• If the meshShader feature is not enabled, stage must not contain PIPELINE_STAGE_2_MESH_SHADER_BIT_EXT
• If the taskShader feature is not enabled, stage must not contain PIPELINE_STAGE_2_TASK_SHADER_BIT_EXT
• If neither the shadingRateImage or attachmentFragmentShadingRate are enabled, stage must not contain PIPELINE_STAGE_2_FRAGMENT_SHADING_RATE_ATTACHMENT_BIT_KHR
• If the subpassShading feature is not enabled, stage must not contain PIPELINE_STAGE_2_SUBPASS_SHADER_BIT_HUAWEI
• If the invocationMask feature is not enabled, stage must not contain PIPELINE_STAGE_2_INVOCATION_MASK_BIT_HUAWEI
• If neither the VK_NV_ray_tracing extension or rayTracingPipeline feature are enabled, stage must not contain PIPELINE_STAGE_2_RAY_TRACING_SHADER_BIT_KHR
• The synchronization2 feature must be enabled
• stage must only include a single pipeline stage
• stage must only include stages valid for the queue family that was used to create the command pool that commandBuffer was allocated from
• queryPool must have been created with a queryType of QUERY_TYPE_TIMESTAMP
• The command pool’s queue family must support a non-zero timestampValidBits
• query must be less than the number of queries in queryPool
• All queries used by the command must be unavailable
• If cmdWriteTimestamp2 is called within a render pass instance, the sum of query and the number of bits set in the current subpass’s view mask must be less than or equal to the number of queries in queryPool

Valid Usage (Implicit)

• commandBuffer must be a valid CommandBuffer handle

• stage must be a valid combination of PipelineStageFlagBits2 values
• queryPool must be a valid QueryPool handle
• commandBuffer must be in the recording state
• The CommandPool that commandBuffer was allocated from must support transfer, graphics, compute, decode, or encode operations
• Both of commandBuffer, and queryPool must have been created, allocated, or retrieved from the same Device

Host Synchronization

• Host access to commandBuffer must be externally synchronized

• Host access to the CommandPool that commandBuffer was allocated from must be externally synchronized

Command Properties

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See Also

VK_KHR_synchronization2, VK_VERSION_1_3, CommandBuffer, PipelineStageFlags2, QueryPool

VkMemoryBarrier2 - Structure specifying a global memory barrier

Description

This structure defines a memory dependency affecting all device memory.

The first synchronization scope and access scope described by this structure include only operations and memory accesses specified by srcStageMask and srcAccessMask.

The second synchronization scope and access scope described by this structure include only operations and memory accesses specified by dstStageMask and dstAccessMask.

Valid Usage

• If the geometryShader feature is not enabled, srcStageMask must not contain PIPELINE_STAGE_2_GEOMETRY_SHADER_BIT

• If the tessellationShader feature is not enabled, srcStageMask must not contain PIPELINE_STAGE_2_TESSELLATION_CONTROL_SHADER_BIT or PIPELINE_STAGE_2_TESSELLATION_EVALUATION_SHADER_BIT
• If the conditionalRendering feature is not enabled, srcStageMask must not contain PIPELINE_STAGE_2_CONDITIONAL_RENDERING_BIT_EXT
• If the fragmentDensityMap feature is not enabled, srcStageMask must not contain PIPELINE_STAGE_2_FRAGMENT_DENSITY_PROCESS_BIT_EXT
• If the transformFeedback feature is not enabled, srcStageMask must not contain PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT
• If the meshShader feature is not enabled, srcStageMask must not contain PIPELINE_STAGE_2_MESH_SHADER_BIT_EXT
• If the taskShader feature is not enabled, srcStageMask must not contain PIPELINE_STAGE_2_TASK_SHADER_BIT_EXT
• If neither the shadingRateImage or attachmentFragmentShadingRate are enabled, srcStageMask must not contain PIPELINE_STAGE_2_FRAGMENT_SHADING_RATE_ATTACHMENT_BIT_KHR
• If the subpassShading feature is not enabled, srcStageMask must not contain PIPELINE_STAGE_2_SUBPASS_SHADER_BIT_HUAWEI
• If the invocationMask feature is not enabled, srcStageMask must not contain PIPELINE_STAGE_2_INVOCATION_MASK_BIT_HUAWEI
• If neither the VK_NV_ray_tracing extension or rayTracingPipeline feature are enabled, srcStageMask must not contain PIPELINE_STAGE_2_RAY_TRACING_SHADER_BIT_KHR
• If srcAccessMask includes ACCESS_2_INDIRECT_COMMAND_READ_BIT, srcStageMask must include PIPELINE_STAGE_2_DRAW_INDIRECT_BIT, PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR, PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If srcAccessMask includes ACCESS_2_INDEX_READ_BIT, srcStageMask must include PIPELINE_STAGE_2_INDEX_INPUT_BIT, PIPELINE_STAGE_2_VERTEX_INPUT_BIT, PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If srcAccessMask includes ACCESS_2_VERTEX_ATTRIBUTE_READ_BIT, srcStageMask must include PIPELINE_STAGE_2_VERTEX_ATTRIBUTE_INPUT_BIT, PIPELINE_STAGE_2_VERTEX_INPUT_BIT, PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If srcAccessMask includes ACCESS_2_INPUT_ATTACHMENT_READ_BIT, srcStageMask must include PIPELINE_STAGE_2_FRAGMENT_SHADER_BIT, PIPELINE_STAGE_2_SUBPASS_SHADER_BIT_HUAWEI, PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If srcAccessMask includes ACCESS_2_UNIFORM_READ_BIT, srcStageMask must include PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, PIPELINE_STAGE_2_ALL_COMMANDS_BIT, or one of the VK_PIPELINE_STAGE_*_SHADER_BIT stages
• If srcAccessMask includes ACCESS_2_SHADER_SAMPLED_READ_BIT, srcStageMask must include PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, PIPELINE_STAGE_2_ALL_COMMANDS_BIT, or one of the VK_PIPELINE_STAGE_*_SHADER_BIT stages
• If srcAccessMask includes ACCESS_2_SHADER_STORAGE_READ_BIT, srcStageMask must include PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, PIPELINE_STAGE_2_ALL_COMMANDS_BIT, or one of the VK_PIPELINE_STAGE_*_SHADER_BIT stages
• If srcAccessMask includes ACCESS_2_SHADER_STORAGE_WRITE_BIT, srcStageMask must include PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, PIPELINE_STAGE_2_ALL_COMMANDS_BIT, or one of the VK_PIPELINE_STAGE_*_SHADER_BIT stages
• If srcAccessMask includes ACCESS_2_SHADER_READ_BIT, srcStageMask must include PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, PIPELINE_STAGE_2_ALL_COMMANDS_BIT, PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR, PIPELINE_STAGE_2_MICROMAP_BUILD_BIT_EXT, or one of the VK_PIPELINE_STAGE_*_SHADER_BIT stages
• If srcAccessMask includes ACCESS_2_SHADER_WRITE_BIT, srcStageMask must include PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, PIPELINE_STAGE_2_ALL_COMMANDS_BIT, or one of the VK_PIPELINE_STAGE_*_SHADER_BIT stages
• If srcAccessMask includes ACCESS_2_COLOR_ATTACHMENT_READ_BIT, srcStageMask must include PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If srcAccessMask includes ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT, srcStageMask must include PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If srcAccessMask includes ACCESS_2_DEPTH_STENCIL_ATTACHMENT_READ_BIT, srcStageMask must include PIPELINE_STAGE_2_EARLY_FRAGMENT_TESTS_BIT, PIPELINE_STAGE_2_LATE_FRAGMENT_TESTS_BIT, PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If srcAccessMask includes ACCESS_2_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT, srcStageMask must include PIPELINE_STAGE_2_EARLY_FRAGMENT_TESTS_BIT, PIPELINE_STAGE_2_LATE_FRAGMENT_TESTS_BIT, PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If srcAccessMask includes ACCESS_2_TRANSFER_READ_BIT, srcStageMask must include PIPELINE_STAGE_2_COPY_BIT, PIPELINE_STAGE_2_BLIT_BIT, PIPELINE_STAGE_2_RESOLVE_BIT, PIPELINE_STAGE_2_ALL_TRANSFER_BIT, PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR, PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_COPY_BIT_KHR, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If srcAccessMask includes ACCESS_2_TRANSFER_WRITE_BIT, srcStageMask must include PIPELINE_STAGE_2_COPY_BIT, PIPELINE_STAGE_2_BLIT_BIT, PIPELINE_STAGE_2_RESOLVE_BIT, PIPELINE_STAGE_2_CLEAR_BIT, PIPELINE_STAGE_2_ALL_TRANSFER_BIT, PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR, or PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_COPY_BIT_KHR, PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If srcAccessMask includes ACCESS_2_HOST_READ_BIT, srcStageMask must include PIPELINE_STAGE_2_HOST_BIT
• If srcAccessMask includes ACCESS_2_HOST_WRITE_BIT, srcStageMask must include PIPELINE_STAGE_2_HOST_BIT
• If srcAccessMask includes ACCESS_2_CONDITIONAL_RENDERING_READ_BIT_EXT, srcStageMask must include PIPELINE_STAGE_2_CONDITIONAL_RENDERING_BIT_EXT, PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If srcAccessMask includes ACCESS_2_FRAGMENT_DENSITY_MAP_READ_BIT_EXT, srcStageMask must include PIPELINE_STAGE_2_FRAGMENT_DENSITY_PROCESS_BIT_EXT, PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If srcAccessMask includes ACCESS_2_TRANSFORM_FEEDBACK_WRITE_BIT_EXT, srcStageMask must include PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT, PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If srcAccessMask includes ACCESS_2_TRANSFORM_FEEDBACK_COUNTER_READ_BIT_EXT, srcStageMask must include PIPELINE_STAGE_2_DRAW_INDIRECT_BIT, PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT, PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If srcAccessMask includes ACCESS_2_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT, srcStageMask must include PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT, PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If srcAccessMask includes ACCESS_2_SHADING_RATE_IMAGE_READ_BIT_NV, srcStageMask must include PIPELINE_STAGE_2_SHADING_RATE_IMAGE_BIT_NV, PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If srcAccessMask includes ACCESS_2_INVOCATION_MASK_READ_BIT_HUAWEI, srcStageMask must include PIPELINE_STAGE_2_INVOCATION_MASK_BIT_HUAWEI
• If srcAccessMask includes ACCESS_2_COMMAND_PREPROCESS_READ_BIT_NV, srcStageMask must include PIPELINE_STAGE_2_COMMAND_PREPROCESS_BIT_NV or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If srcAccessMask includes ACCESS_2_COMMAND_PREPROCESS_WRITE_BIT_NV, srcStageMask must include PIPELINE_STAGE_2_COMMAND_PREPROCESS_BIT_NV or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If srcAccessMask includes ACCESS_2_COLOR_ATTACHMENT_READ_NONCOHERENT_BIT_EXT, srcStageMask must include PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If srcAccessMask includes ACCESS_2_ACCELERATION_STRUCTURE_READ_BIT_KHR, srcStageMask must include PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR, PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_COPY_BIT_KHR, PIPELINE_STAGE_2_ALL_COMMANDS_BIT, or one of the VK_PIPELINE_STAGE_*_SHADER_BIT stages
• If srcAccessMask includes ACCESS_2_ACCELERATION_STRUCTURE_WRITE_BIT_KHR, srcStageMask must include PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_COPY_BIT_KHR, PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If the rayQuery feature is not enabled and srcAccessMask includes ACCESS_2_ACCELERATION_STRUCTURE_READ_BIT_KHR, srcStageMask must not include any of the VK_PIPELINE_STAGE_*_SHADER_BIT stages except PIPELINE_STAGE_2_RAY_TRACING_SHADER_BIT_KHR
• If srcAccessMask includes ACCESS_2_SHADER_BINDING_TABLE_READ_BIT_KHR, srcStageMask must include PIPELINE_STAGE_2_ALL_COMMANDS_BIT or PIPELINE_STAGE_2_RAY_TRACING_SHADER_BIT_KHR
• If srcAccessMask includes VK_ACCESS_2_VIDEO_DECODE_READ_BIT_KHR, srcStageMask must include VK_PIPELINE_STAGE_2_VIDEO_DECODE_BIT_KHR
• If srcAccessMask includes VK_ACCESS_2_VIDEO_DECODE_WRITE_BIT_KHR, srcStageMask must include VK_PIPELINE_STAGE_2_VIDEO_DECODE_BIT_KHR
• If srcAccessMask includes VK_ACCESS_2_VIDEO_ENCODE_READ_BIT_KHR, srcStageMask must include VK_PIPELINE_STAGE_2_VIDEO_ENCODE_BIT_KHR
• If srcAccessMask includes VK_ACCESS_2_VIDEO_ENCODE_WRITE_BIT_KHR, srcStageMask must include VK_PIPELINE_STAGE_2_VIDEO_ENCODE_BIT_KHR
• If srcAccessMask includes ACCESS_2_OPTICAL_FLOW_READ_BIT_NV, srcStageMask must include PIPELINE_STAGE_2_OPTICAL_FLOW_BIT_NV
• If srcAccessMask includes ACCESS_2_OPTICAL_FLOW_WRITE_BIT_NV, srcStageMask must include PIPELINE_STAGE_2_OPTICAL_FLOW_BIT_NV
• If srcAccessMask includes ACCESS_2_MICROMAP_WRITE_BIT_EXT, srcStageMask must include PIPELINE_STAGE_2_MICROMAP_BUILD_BIT_EXT
• If srcAccessMask includes ACCESS_2_MICROMAP_READ_BIT_EXT, srcStageMask must include PIPELINE_STAGE_2_MICROMAP_BUILD_BIT_EXT or PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR
• If srcAccessMask includes ACCESS_2_DESCRIPTOR_BUFFER_READ_BIT_EXT, srcStageMask must include PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, PIPELINE_STAGE_2_ALL_COMMANDS_BIT, or one of VK_PIPELINE_STAGE_*_SHADER_BIT stages
• If the geometryShader feature is not enabled, dstStageMask must not contain PIPELINE_STAGE_2_GEOMETRY_SHADER_BIT
• If the tessellationShader feature is not enabled, dstStageMask must not contain PIPELINE_STAGE_2_TESSELLATION_CONTROL_SHADER_BIT or PIPELINE_STAGE_2_TESSELLATION_EVALUATION_SHADER_BIT
• If the conditionalRendering feature is not enabled, dstStageMask must not contain PIPELINE_STAGE_2_CONDITIONAL_RENDERING_BIT_EXT
• If the fragmentDensityMap feature is not enabled, dstStageMask must not contain PIPELINE_STAGE_2_FRAGMENT_DENSITY_PROCESS_BIT_EXT
• If the transformFeedback feature is not enabled, dstStageMask must not contain PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT
• If the meshShader feature is not enabled, dstStageMask must not contain PIPELINE_STAGE_2_MESH_SHADER_BIT_EXT
• If the taskShader feature is not enabled, dstStageMask must not contain PIPELINE_STAGE_2_TASK_SHADER_BIT_EXT
• If neither the shadingRateImage or attachmentFragmentShadingRate are enabled, dstStageMask must not contain PIPELINE_STAGE_2_FRAGMENT_SHADING_RATE_ATTACHMENT_BIT_KHR
• If the subpassShading feature is not enabled, dstStageMask must not contain PIPELINE_STAGE_2_SUBPASS_SHADER_BIT_HUAWEI
• If the invocationMask feature is not enabled, dstStageMask must not contain PIPELINE_STAGE_2_INVOCATION_MASK_BIT_HUAWEI
• If neither the VK_NV_ray_tracing extension or rayTracingPipeline feature are enabled, dstStageMask must not contain PIPELINE_STAGE_2_RAY_TRACING_SHADER_BIT_KHR
• If dstAccessMask includes ACCESS_2_INDIRECT_COMMAND_READ_BIT, dstStageMask must include PIPELINE_STAGE_2_DRAW_INDIRECT_BIT, PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR, PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If dstAccessMask includes ACCESS_2_INDEX_READ_BIT, dstStageMask must include PIPELINE_STAGE_2_INDEX_INPUT_BIT, PIPELINE_STAGE_2_VERTEX_INPUT_BIT, PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If dstAccessMask includes ACCESS_2_VERTEX_ATTRIBUTE_READ_BIT, dstStageMask must include PIPELINE_STAGE_2_VERTEX_ATTRIBUTE_INPUT_BIT, PIPELINE_STAGE_2_VERTEX_INPUT_BIT, PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If dstAccessMask includes ACCESS_2_INPUT_ATTACHMENT_READ_BIT, dstStageMask must include PIPELINE_STAGE_2_FRAGMENT_SHADER_BIT, PIPELINE_STAGE_2_SUBPASS_SHADER_BIT_HUAWEI, PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If dstAccessMask includes ACCESS_2_UNIFORM_READ_BIT, dstStageMask must include PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, PIPELINE_STAGE_2_ALL_COMMANDS_BIT, or one of the VK_PIPELINE_STAGE_*_SHADER_BIT stages
• If dstAccessMask includes ACCESS_2_SHADER_SAMPLED_READ_BIT, dstStageMask must include PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, PIPELINE_STAGE_2_ALL_COMMANDS_BIT, or one of the VK_PIPELINE_STAGE_*_SHADER_BIT stages
• If dstAccessMask includes ACCESS_2_SHADER_STORAGE_READ_BIT, dstStageMask must include PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, PIPELINE_STAGE_2_ALL_COMMANDS_BIT, or one of the VK_PIPELINE_STAGE_*_SHADER_BIT stages
• If dstAccessMask includes ACCESS_2_SHADER_STORAGE_WRITE_BIT, dstStageMask must include PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, PIPELINE_STAGE_2_ALL_COMMANDS_BIT, or one of the VK_PIPELINE_STAGE_*_SHADER_BIT stages
• If dstAccessMask includes ACCESS_2_SHADER_READ_BIT, dstStageMask must include PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, PIPELINE_STAGE_2_ALL_COMMANDS_BIT, PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR, PIPELINE_STAGE_2_MICROMAP_BUILD_BIT_EXT, or one of the VK_PIPELINE_STAGE_*_SHADER_BIT stages
• If dstAccessMask includes ACCESS_2_SHADER_WRITE_BIT, dstStageMask must include PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, PIPELINE_STAGE_2_ALL_COMMANDS_BIT, or one of the VK_PIPELINE_STAGE_*_SHADER_BIT stages
• If dstAccessMask includes ACCESS_2_COLOR_ATTACHMENT_READ_BIT, dstStageMask must include PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If dstAccessMask includes ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT, dstStageMask must include PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If dstAccessMask includes ACCESS_2_DEPTH_STENCIL_ATTACHMENT_READ_BIT, dstStageMask must include PIPELINE_STAGE_2_EARLY_FRAGMENT_TESTS_BIT, PIPELINE_STAGE_2_LATE_FRAGMENT_TESTS_BIT, PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If dstAccessMask includes ACCESS_2_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT, dstStageMask must include PIPELINE_STAGE_2_EARLY_FRAGMENT_TESTS_BIT, PIPELINE_STAGE_2_LATE_FRAGMENT_TESTS_BIT, PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If dstAccessMask includes ACCESS_2_TRANSFER_READ_BIT, dstStageMask must include PIPELINE_STAGE_2_COPY_BIT, PIPELINE_STAGE_2_BLIT_BIT, PIPELINE_STAGE_2_RESOLVE_BIT, PIPELINE_STAGE_2_ALL_TRANSFER_BIT, PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR, PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_COPY_BIT_KHR, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If dstAccessMask includes ACCESS_2_TRANSFER_WRITE_BIT, dstStageMask must include PIPELINE_STAGE_2_COPY_BIT, PIPELINE_STAGE_2_BLIT_BIT, PIPELINE_STAGE_2_RESOLVE_BIT, PIPELINE_STAGE_2_CLEAR_BIT, PIPELINE_STAGE_2_ALL_TRANSFER_BIT, PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR, or PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_COPY_BIT_KHR, PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If dstAccessMask includes ACCESS_2_HOST_READ_BIT, dstStageMask must include PIPELINE_STAGE_2_HOST_BIT
• If dstAccessMask includes ACCESS_2_HOST_WRITE_BIT, dstStageMask must include PIPELINE_STAGE_2_HOST_BIT
• If dstAccessMask includes ACCESS_2_CONDITIONAL_RENDERING_READ_BIT_EXT, dstStageMask must include PIPELINE_STAGE_2_CONDITIONAL_RENDERING_BIT_EXT, PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If dstAccessMask includes ACCESS_2_FRAGMENT_DENSITY_MAP_READ_BIT_EXT, dstStageMask must include PIPELINE_STAGE_2_FRAGMENT_DENSITY_PROCESS_BIT_EXT, PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If dstAccessMask includes ACCESS_2_TRANSFORM_FEEDBACK_WRITE_BIT_EXT, dstStageMask must include PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT, PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If dstAccessMask includes ACCESS_2_TRANSFORM_FEEDBACK_COUNTER_READ_BIT_EXT, dstStageMask must include PIPELINE_STAGE_2_DRAW_INDIRECT_BIT, PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT, PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If dstAccessMask includes ACCESS_2_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT, dstStageMask must include PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT, PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If dstAccessMask includes ACCESS_2_SHADING_RATE_IMAGE_READ_BIT_NV, dstStageMask must include PIPELINE_STAGE_2_SHADING_RATE_IMAGE_BIT_NV, PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If dstAccessMask includes ACCESS_2_INVOCATION_MASK_READ_BIT_HUAWEI, dstStageMask must include PIPELINE_STAGE_2_INVOCATION_MASK_BIT_HUAWEI
• If dstAccessMask includes ACCESS_2_COMMAND_PREPROCESS_READ_BIT_NV, dstStageMask must include PIPELINE_STAGE_2_COMMAND_PREPROCESS_BIT_NV or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If dstAccessMask includes ACCESS_2_COMMAND_PREPROCESS_WRITE_BIT_NV, dstStageMask must include PIPELINE_STAGE_2_COMMAND_PREPROCESS_BIT_NV or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If dstAccessMask includes ACCESS_2_COLOR_ATTACHMENT_READ_NONCOHERENT_BIT_EXT, dstStageMask must include PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If dstAccessMask includes ACCESS_2_ACCELERATION_STRUCTURE_READ_BIT_KHR, dstStageMask must include PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR, PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_COPY_BIT_KHR, PIPELINE_STAGE_2_ALL_COMMANDS_BIT, or one of the VK_PIPELINE_STAGE_*_SHADER_BIT stages
• If dstAccessMask includes ACCESS_2_ACCELERATION_STRUCTURE_WRITE_BIT_KHR, dstStageMask must include PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_COPY_BIT_KHR, PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If the rayQuery feature is not enabled and dstAccessMask includes ACCESS_2_ACCELERATION_STRUCTURE_READ_BIT_KHR, dstStageMask must not include any of the VK_PIPELINE_STAGE_*_SHADER_BIT stages except PIPELINE_STAGE_2_RAY_TRACING_SHADER_BIT_KHR
• If dstAccessMask includes ACCESS_2_SHADER_BINDING_TABLE_READ_BIT_KHR, dstStageMask must include PIPELINE_STAGE_2_ALL_COMMANDS_BIT or PIPELINE_STAGE_2_RAY_TRACING_SHADER_BIT_KHR
• If dstAccessMask includes VK_ACCESS_2_VIDEO_DECODE_READ_BIT_KHR, dstStageMask must include VK_PIPELINE_STAGE_2_VIDEO_DECODE_BIT_KHR
• If dstAccessMask includes VK_ACCESS_2_VIDEO_DECODE_WRITE_BIT_KHR, dstStageMask must include VK_PIPELINE_STAGE_2_VIDEO_DECODE_BIT_KHR
• If dstAccessMask includes VK_ACCESS_2_VIDEO_ENCODE_READ_BIT_KHR, dstStageMask must include VK_PIPELINE_STAGE_2_VIDEO_ENCODE_BIT_KHR
• If dstAccessMask includes VK_ACCESS_2_VIDEO_ENCODE_WRITE_BIT_KHR, dstStageMask must include VK_PIPELINE_STAGE_2_VIDEO_ENCODE_BIT_KHR
• If dstAccessMask includes ACCESS_2_OPTICAL_FLOW_READ_BIT_NV, dstStageMask must include PIPELINE_STAGE_2_OPTICAL_FLOW_BIT_NV
• If dstAccessMask includes ACCESS_2_OPTICAL_FLOW_WRITE_BIT_NV, dstStageMask must include PIPELINE_STAGE_2_OPTICAL_FLOW_BIT_NV
• If dstAccessMask includes ACCESS_2_MICROMAP_WRITE_BIT_EXT, dstStageMask must include PIPELINE_STAGE_2_MICROMAP_BUILD_BIT_EXT
• If dstAccessMask includes ACCESS_2_MICROMAP_READ_BIT_EXT, dstStageMask must include PIPELINE_STAGE_2_MICROMAP_BUILD_BIT_EXT or PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR
• If dstAccessMask includes ACCESS_2_DESCRIPTOR_BUFFER_READ_BIT_EXT, dstStageMask must include PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, PIPELINE_STAGE_2_ALL_COMMANDS_BIT, or one of VK_PIPELINE_STAGE_*_SHADER_BIT stages

Valid Usage (Implicit)

• sType must be STRUCTURE_TYPE_MEMORY_BARRIER_2

• srcStageMask must be a valid combination of PipelineStageFlagBits2 values
• srcAccessMask must be a valid combination of AccessFlagBits2 values
• dstStageMask must be a valid combination of PipelineStageFlagBits2 values
• dstAccessMask must be a valid combination of AccessFlagBits2 values

See Also

VK_KHR_synchronization2, VK_VERSION_1_3, AccessFlags2, DependencyInfo, PipelineStageFlags2, StructureType

VkImageMemoryBarrier2 - Structure specifying an image memory barrier

Description

This structure defines a memory dependency limited to an image subresource range, and can define a queue family transfer operation and image layout transition for that subresource range.

The first synchronization scope and access scope described by this structure include only operations and memory accesses specified by srcStageMask and srcAccessMask.

The second synchronization scope and access scope described by this structure include only operations and memory accesses specified by dstStageMask and dstAccessMask.

Both access scopes are limited to only memory accesses to image in the subresource range defined by subresourceRange.

If image was created with SHARING_MODE_EXCLUSIVE, and srcQueueFamilyIndex is not equal to dstQueueFamilyIndex, this memory barrier defines a queue family transfer operation. When executed on a queue in the family identified by srcQueueFamilyIndex, this barrier defines a queue family release operation for the specified image subresource range, and the second synchronization and access scopes do not synchronize operations on that queue. When executed on a queue in the family identified by dstQueueFamilyIndex, this barrier defines a queue family acquire operation for the specified image subresource range, and the first synchronization and access scopes do not synchronize operations on that queue.

A queue family transfer operation is also defined if the values are not equal, and either is one of the special queue family values reserved for external memory ownership transfers, as described in https://registry.khronos.org/vulkan/specs/1.3-extensions/html/vkspec.html#synchronization-queue-transfers. A queue family release operation is defined when dstQueueFamilyIndex is one of those values, and a queue family acquire operation is defined when srcQueueFamilyIndex is one of those values.

If oldLayout is not equal to newLayout, then the memory barrier defines an image layout transition for the specified image subresource range. If this memory barrier defines a queue family transfer operation, the layout transition is only executed once between the queues.

Note

When the old and new layout are equal, the layout values are ignored - data is preserved no matter what values are specified, or what layout the image is currently in.

If image has a multi-planar format and the image is disjoint, then including IMAGE_ASPECT_COLOR_BIT in the aspectMask member of subresourceRange is equivalent to including IMAGE_ASPECT_PLANE_0_BIT, IMAGE_ASPECT_PLANE_1_BIT, and (for three-plane formats only) IMAGE_ASPECT_PLANE_2_BIT.

Valid Usage

• If the geometryShader feature is not enabled, srcStageMask must not contain PIPELINE_STAGE_2_GEOMETRY_SHADER_BIT

• If the tessellationShader feature is not enabled, srcStageMask must not contain PIPELINE_STAGE_2_TESSELLATION_CONTROL_SHADER_BIT or PIPELINE_STAGE_2_TESSELLATION_EVALUATION_SHADER_BIT
• If the conditionalRendering feature is not enabled, srcStageMask must not contain PIPELINE_STAGE_2_CONDITIONAL_RENDERING_BIT_EXT
• If the fragmentDensityMap feature is not enabled, srcStageMask must not contain PIPELINE_STAGE_2_FRAGMENT_DENSITY_PROCESS_BIT_EXT
• If the transformFeedback feature is not enabled, srcStageMask must not contain PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT
• If the meshShader feature is not enabled, srcStageMask must not contain PIPELINE_STAGE_2_MESH_SHADER_BIT_EXT
• If the taskShader feature is not enabled, srcStageMask must not contain PIPELINE_STAGE_2_TASK_SHADER_BIT_EXT
• If neither the shadingRateImage or attachmentFragmentShadingRate are enabled, srcStageMask must not contain PIPELINE_STAGE_2_FRAGMENT_SHADING_RATE_ATTACHMENT_BIT_KHR
• If the subpassShading feature is not enabled, srcStageMask must not contain PIPELINE_STAGE_2_SUBPASS_SHADER_BIT_HUAWEI
• If the invocationMask feature is not enabled, srcStageMask must not contain PIPELINE_STAGE_2_INVOCATION_MASK_BIT_HUAWEI
• If neither the VK_NV_ray_tracing extension or rayTracingPipeline feature are enabled, srcStageMask must not contain PIPELINE_STAGE_2_RAY_TRACING_SHADER_BIT_KHR
• If srcAccessMask includes ACCESS_2_INDIRECT_COMMAND_READ_BIT, srcStageMask must include PIPELINE_STAGE_2_DRAW_INDIRECT_BIT, PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR, PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If srcAccessMask includes ACCESS_2_INDEX_READ_BIT, srcStageMask must include PIPELINE_STAGE_2_INDEX_INPUT_BIT, PIPELINE_STAGE_2_VERTEX_INPUT_BIT, PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If srcAccessMask includes ACCESS_2_VERTEX_ATTRIBUTE_READ_BIT, srcStageMask must include PIPELINE_STAGE_2_VERTEX_ATTRIBUTE_INPUT_BIT, PIPELINE_STAGE_2_VERTEX_INPUT_BIT, PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If srcAccessMask includes ACCESS_2_INPUT_ATTACHMENT_READ_BIT, srcStageMask must include PIPELINE_STAGE_2_FRAGMENT_SHADER_BIT, PIPELINE_STAGE_2_SUBPASS_SHADER_BIT_HUAWEI, PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If srcAccessMask includes ACCESS_2_UNIFORM_READ_BIT, srcStageMask must include PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, PIPELINE_STAGE_2_ALL_COMMANDS_BIT, or one of the VK_PIPELINE_STAGE_*_SHADER_BIT stages
• If srcAccessMask includes ACCESS_2_SHADER_SAMPLED_READ_BIT, srcStageMask must include PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, PIPELINE_STAGE_2_ALL_COMMANDS_BIT, or one of the VK_PIPELINE_STAGE_*_SHADER_BIT stages
• If srcAccessMask includes ACCESS_2_SHADER_STORAGE_READ_BIT, srcStageMask must include PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, PIPELINE_STAGE_2_ALL_COMMANDS_BIT, or one of the VK_PIPELINE_STAGE_*_SHADER_BIT stages
• If srcAccessMask includes ACCESS_2_SHADER_STORAGE_WRITE_BIT, srcStageMask must include PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, PIPELINE_STAGE_2_ALL_COMMANDS_BIT, or one of the VK_PIPELINE_STAGE_*_SHADER_BIT stages
• If srcAccessMask includes ACCESS_2_SHADER_READ_BIT, srcStageMask must include PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, PIPELINE_STAGE_2_ALL_COMMANDS_BIT, PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR, PIPELINE_STAGE_2_MICROMAP_BUILD_BIT_EXT, or one of the VK_PIPELINE_STAGE_*_SHADER_BIT stages
• If srcAccessMask includes ACCESS_2_SHADER_WRITE_BIT, srcStageMask must include PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, PIPELINE_STAGE_2_ALL_COMMANDS_BIT, or one of the VK_PIPELINE_STAGE_*_SHADER_BIT stages
• If srcAccessMask includes ACCESS_2_COLOR_ATTACHMENT_READ_BIT, srcStageMask must include PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If srcAccessMask includes ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT, srcStageMask must include PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If srcAccessMask includes ACCESS_2_DEPTH_STENCIL_ATTACHMENT_READ_BIT, srcStageMask must include PIPELINE_STAGE_2_EARLY_FRAGMENT_TESTS_BIT, PIPELINE_STAGE_2_LATE_FRAGMENT_TESTS_BIT, PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If srcAccessMask includes ACCESS_2_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT, srcStageMask must include PIPELINE_STAGE_2_EARLY_FRAGMENT_TESTS_BIT, PIPELINE_STAGE_2_LATE_FRAGMENT_TESTS_BIT, PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If srcAccessMask includes ACCESS_2_TRANSFER_READ_BIT, srcStageMask must include PIPELINE_STAGE_2_COPY_BIT, PIPELINE_STAGE_2_BLIT_BIT, PIPELINE_STAGE_2_RESOLVE_BIT, PIPELINE_STAGE_2_ALL_TRANSFER_BIT, PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR, PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_COPY_BIT_KHR, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If srcAccessMask includes ACCESS_2_TRANSFER_WRITE_BIT, srcStageMask must include PIPELINE_STAGE_2_COPY_BIT, PIPELINE_STAGE_2_BLIT_BIT, PIPELINE_STAGE_2_RESOLVE_BIT, PIPELINE_STAGE_2_CLEAR_BIT, PIPELINE_STAGE_2_ALL_TRANSFER_BIT, PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR, or PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_COPY_BIT_KHR, PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If srcAccessMask includes ACCESS_2_HOST_READ_BIT, srcStageMask must include PIPELINE_STAGE_2_HOST_BIT
• If srcAccessMask includes ACCESS_2_HOST_WRITE_BIT, srcStageMask must include PIPELINE_STAGE_2_HOST_BIT
• If srcAccessMask includes ACCESS_2_CONDITIONAL_RENDERING_READ_BIT_EXT, srcStageMask must include PIPELINE_STAGE_2_CONDITIONAL_RENDERING_BIT_EXT, PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If srcAccessMask includes ACCESS_2_FRAGMENT_DENSITY_MAP_READ_BIT_EXT, srcStageMask must include PIPELINE_STAGE_2_FRAGMENT_DENSITY_PROCESS_BIT_EXT, PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If srcAccessMask includes ACCESS_2_TRANSFORM_FEEDBACK_WRITE_BIT_EXT, srcStageMask must include PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT, PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If srcAccessMask includes ACCESS_2_TRANSFORM_FEEDBACK_COUNTER_READ_BIT_EXT, srcStageMask must include PIPELINE_STAGE_2_DRAW_INDIRECT_BIT, PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT, PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If srcAccessMask includes ACCESS_2_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT, srcStageMask must include PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT, PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If srcAccessMask includes ACCESS_2_SHADING_RATE_IMAGE_READ_BIT_NV, srcStageMask must include PIPELINE_STAGE_2_SHADING_RATE_IMAGE_BIT_NV, PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If srcAccessMask includes ACCESS_2_INVOCATION_MASK_READ_BIT_HUAWEI, srcStageMask must include PIPELINE_STAGE_2_INVOCATION_MASK_BIT_HUAWEI
• If srcAccessMask includes ACCESS_2_COMMAND_PREPROCESS_READ_BIT_NV, srcStageMask must include PIPELINE_STAGE_2_COMMAND_PREPROCESS_BIT_NV or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If srcAccessMask includes ACCESS_2_COMMAND_PREPROCESS_WRITE_BIT_NV, srcStageMask must include PIPELINE_STAGE_2_COMMAND_PREPROCESS_BIT_NV or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If srcAccessMask includes ACCESS_2_COLOR_ATTACHMENT_READ_NONCOHERENT_BIT_EXT, srcStageMask must include PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If srcAccessMask includes ACCESS_2_ACCELERATION_STRUCTURE_READ_BIT_KHR, srcStageMask must include PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR, PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_COPY_BIT_KHR, PIPELINE_STAGE_2_ALL_COMMANDS_BIT, or one of the VK_PIPELINE_STAGE_*_SHADER_BIT stages
• If srcAccessMask includes ACCESS_2_ACCELERATION_STRUCTURE_WRITE_BIT_KHR, srcStageMask must include PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_COPY_BIT_KHR, PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If the rayQuery feature is not enabled and srcAccessMask includes ACCESS_2_ACCELERATION_STRUCTURE_READ_BIT_KHR, srcStageMask must not include any of the VK_PIPELINE_STAGE_*_SHADER_BIT stages except PIPELINE_STAGE_2_RAY_TRACING_SHADER_BIT_KHR
• If srcAccessMask includes ACCESS_2_SHADER_BINDING_TABLE_READ_BIT_KHR, srcStageMask must include PIPELINE_STAGE_2_ALL_COMMANDS_BIT or PIPELINE_STAGE_2_RAY_TRACING_SHADER_BIT_KHR
• If srcAccessMask includes VK_ACCESS_2_VIDEO_DECODE_READ_BIT_KHR, srcStageMask must include VK_PIPELINE_STAGE_2_VIDEO_DECODE_BIT_KHR
• If srcAccessMask includes VK_ACCESS_2_VIDEO_DECODE_WRITE_BIT_KHR, srcStageMask must include VK_PIPELINE_STAGE_2_VIDEO_DECODE_BIT_KHR
• If srcAccessMask includes VK_ACCESS_2_VIDEO_ENCODE_READ_BIT_KHR, srcStageMask must include VK_PIPELINE_STAGE_2_VIDEO_ENCODE_BIT_KHR
• If srcAccessMask includes VK_ACCESS_2_VIDEO_ENCODE_WRITE_BIT_KHR, srcStageMask must include VK_PIPELINE_STAGE_2_VIDEO_ENCODE_BIT_KHR
• If srcAccessMask includes ACCESS_2_OPTICAL_FLOW_READ_BIT_NV, srcStageMask must include PIPELINE_STAGE_2_OPTICAL_FLOW_BIT_NV
• If srcAccessMask includes ACCESS_2_OPTICAL_FLOW_WRITE_BIT_NV, srcStageMask must include PIPELINE_STAGE_2_OPTICAL_FLOW_BIT_NV
• If srcAccessMask includes ACCESS_2_MICROMAP_WRITE_BIT_EXT, srcStageMask must include PIPELINE_STAGE_2_MICROMAP_BUILD_BIT_EXT
• If srcAccessMask includes ACCESS_2_MICROMAP_READ_BIT_EXT, srcStageMask must include PIPELINE_STAGE_2_MICROMAP_BUILD_BIT_EXT or PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR
• If srcAccessMask includes ACCESS_2_DESCRIPTOR_BUFFER_READ_BIT_EXT, srcStageMask must include PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, PIPELINE_STAGE_2_ALL_COMMANDS_BIT, or one of VK_PIPELINE_STAGE_*_SHADER_BIT stages
• If the geometryShader feature is not enabled, dstStageMask must not contain PIPELINE_STAGE_2_GEOMETRY_SHADER_BIT
• If the tessellationShader feature is not enabled, dstStageMask must not contain PIPELINE_STAGE_2_TESSELLATION_CONTROL_SHADER_BIT or PIPELINE_STAGE_2_TESSELLATION_EVALUATION_SHADER_BIT
• If the conditionalRendering feature is not enabled, dstStageMask must not contain PIPELINE_STAGE_2_CONDITIONAL_RENDERING_BIT_EXT
• If the fragmentDensityMap feature is not enabled, dstStageMask must not contain PIPELINE_STAGE_2_FRAGMENT_DENSITY_PROCESS_BIT_EXT
• If the transformFeedback feature is not enabled, dstStageMask must not contain PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT
• If the meshShader feature is not enabled, dstStageMask must not contain PIPELINE_STAGE_2_MESH_SHADER_BIT_EXT
• If the taskShader feature is not enabled, dstStageMask must not contain PIPELINE_STAGE_2_TASK_SHADER_BIT_EXT
• If neither the shadingRateImage or attachmentFragmentShadingRate are enabled, dstStageMask must not contain PIPELINE_STAGE_2_FRAGMENT_SHADING_RATE_ATTACHMENT_BIT_KHR
• If the subpassShading feature is not enabled, dstStageMask must not contain PIPELINE_STAGE_2_SUBPASS_SHADER_BIT_HUAWEI
• If the invocationMask feature is not enabled, dstStageMask must not contain PIPELINE_STAGE_2_INVOCATION_MASK_BIT_HUAWEI
• If neither the VK_NV_ray_tracing extension or rayTracingPipeline feature are enabled, dstStageMask must not contain PIPELINE_STAGE_2_RAY_TRACING_SHADER_BIT_KHR
• If dstAccessMask includes ACCESS_2_INDIRECT_COMMAND_READ_BIT, dstStageMask must include PIPELINE_STAGE_2_DRAW_INDIRECT_BIT, PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR, PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If dstAccessMask includes ACCESS_2_INDEX_READ_BIT, dstStageMask must include PIPELINE_STAGE_2_INDEX_INPUT_BIT, PIPELINE_STAGE_2_VERTEX_INPUT_BIT, PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If dstAccessMask includes ACCESS_2_VERTEX_ATTRIBUTE_READ_BIT, dstStageMask must include PIPELINE_STAGE_2_VERTEX_ATTRIBUTE_INPUT_BIT, PIPELINE_STAGE_2_VERTEX_INPUT_BIT, PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If dstAccessMask includes ACCESS_2_INPUT_ATTACHMENT_READ_BIT, dstStageMask must include PIPELINE_STAGE_2_FRAGMENT_SHADER_BIT, PIPELINE_STAGE_2_SUBPASS_SHADER_BIT_HUAWEI, PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If dstAccessMask includes ACCESS_2_UNIFORM_READ_BIT, dstStageMask must include PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, PIPELINE_STAGE_2_ALL_COMMANDS_BIT, or one of the VK_PIPELINE_STAGE_*_SHADER_BIT stages
• If dstAccessMask includes ACCESS_2_SHADER_SAMPLED_READ_BIT, dstStageMask must include PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, PIPELINE_STAGE_2_ALL_COMMANDS_BIT, or one of the VK_PIPELINE_STAGE_*_SHADER_BIT stages
• If dstAccessMask includes ACCESS_2_SHADER_STORAGE_READ_BIT, dstStageMask must include PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, PIPELINE_STAGE_2_ALL_COMMANDS_BIT, or one of the VK_PIPELINE_STAGE_*_SHADER_BIT stages
• If dstAccessMask includes ACCESS_2_SHADER_STORAGE_WRITE_BIT, dstStageMask must include PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, PIPELINE_STAGE_2_ALL_COMMANDS_BIT, or one of the VK_PIPELINE_STAGE_*_SHADER_BIT stages
• If dstAccessMask includes ACCESS_2_SHADER_READ_BIT, dstStageMask must include PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, PIPELINE_STAGE_2_ALL_COMMANDS_BIT, PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR, PIPELINE_STAGE_2_MICROMAP_BUILD_BIT_EXT, or one of the VK_PIPELINE_STAGE_*_SHADER_BIT stages
• If dstAccessMask includes ACCESS_2_SHADER_WRITE_BIT, dstStageMask must include PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, PIPELINE_STAGE_2_ALL_COMMANDS_BIT, or one of the VK_PIPELINE_STAGE_*_SHADER_BIT stages
• If dstAccessMask includes ACCESS_2_COLOR_ATTACHMENT_READ_BIT, dstStageMask must include PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If dstAccessMask includes ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT, dstStageMask must include PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If dstAccessMask includes ACCESS_2_DEPTH_STENCIL_ATTACHMENT_READ_BIT, dstStageMask must include PIPELINE_STAGE_2_EARLY_FRAGMENT_TESTS_BIT, PIPELINE_STAGE_2_LATE_FRAGMENT_TESTS_BIT, PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If dstAccessMask includes ACCESS_2_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT, dstStageMask must include PIPELINE_STAGE_2_EARLY_FRAGMENT_TESTS_BIT, PIPELINE_STAGE_2_LATE_FRAGMENT_TESTS_BIT, PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If dstAccessMask includes ACCESS_2_TRANSFER_READ_BIT, dstStageMask must include PIPELINE_STAGE_2_COPY_BIT, PIPELINE_STAGE_2_BLIT_BIT, PIPELINE_STAGE_2_RESOLVE_BIT, PIPELINE_STAGE_2_ALL_TRANSFER_BIT, PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR, PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_COPY_BIT_KHR, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If dstAccessMask includes ACCESS_2_TRANSFER_WRITE_BIT, dstStageMask must include PIPELINE_STAGE_2_COPY_BIT, PIPELINE_STAGE_2_BLIT_BIT, PIPELINE_STAGE_2_RESOLVE_BIT, PIPELINE_STAGE_2_CLEAR_BIT, PIPELINE_STAGE_2_ALL_TRANSFER_BIT, PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR, or PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_COPY_BIT_KHR, PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If dstAccessMask includes ACCESS_2_HOST_READ_BIT, dstStageMask must include PIPELINE_STAGE_2_HOST_BIT
• If dstAccessMask includes ACCESS_2_HOST_WRITE_BIT, dstStageMask must include PIPELINE_STAGE_2_HOST_BIT
• If dstAccessMask includes ACCESS_2_CONDITIONAL_RENDERING_READ_BIT_EXT, dstStageMask must include PIPELINE_STAGE_2_CONDITIONAL_RENDERING_BIT_EXT, PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If dstAccessMask includes ACCESS_2_FRAGMENT_DENSITY_MAP_READ_BIT_EXT, dstStageMask must include PIPELINE_STAGE_2_FRAGMENT_DENSITY_PROCESS_BIT_EXT, PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If dstAccessMask includes ACCESS_2_TRANSFORM_FEEDBACK_WRITE_BIT_EXT, dstStageMask must include PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT, PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If dstAccessMask includes ACCESS_2_TRANSFORM_FEEDBACK_COUNTER_READ_BIT_EXT, dstStageMask must include PIPELINE_STAGE_2_DRAW_INDIRECT_BIT, PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT, PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If dstAccessMask includes ACCESS_2_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT, dstStageMask must include PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT, PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If dstAccessMask includes ACCESS_2_SHADING_RATE_IMAGE_READ_BIT_NV, dstStageMask must include PIPELINE_STAGE_2_SHADING_RATE_IMAGE_BIT_NV, PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If dstAccessMask includes ACCESS_2_INVOCATION_MASK_READ_BIT_HUAWEI, dstStageMask must include PIPELINE_STAGE_2_INVOCATION_MASK_BIT_HUAWEI
• If dstAccessMask includes ACCESS_2_COMMAND_PREPROCESS_READ_BIT_NV, dstStageMask must include PIPELINE_STAGE_2_COMMAND_PREPROCESS_BIT_NV or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If dstAccessMask includes ACCESS_2_COMMAND_PREPROCESS_WRITE_BIT_NV, dstStageMask must include PIPELINE_STAGE_2_COMMAND_PREPROCESS_BIT_NV or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If dstAccessMask includes ACCESS_2_COLOR_ATTACHMENT_READ_NONCOHERENT_BIT_EXT, dstStageMask must include PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If dstAccessMask includes ACCESS_2_ACCELERATION_STRUCTURE_READ_BIT_KHR, dstStageMask must include PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR, PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_COPY_BIT_KHR, PIPELINE_STAGE_2_ALL_COMMANDS_BIT, or one of the VK_PIPELINE_STAGE_*_SHADER_BIT stages
• If dstAccessMask includes ACCESS_2_ACCELERATION_STRUCTURE_WRITE_BIT_KHR, dstStageMask must include PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_COPY_BIT_KHR, PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR or PIPELINE_STAGE_2_ALL_COMMANDS_BIT
• If the rayQuery feature is not enabled and dstAccessMask includes ACCESS_2_ACCELERATION_STRUCTURE_READ_BIT_KHR, dstStageMask must not include any of the VK_PIPELINE_STAGE_*_SHADER_BIT stages except PIPELINE_STAGE_2_RAY_TRACING_SHADER_BIT_KHR
• If dstAccessMask includes ACCESS_2_SHADER_BINDING_TABLE_READ_BIT_KHR, dstStageMask must include PIPELINE_STAGE_2_ALL_COMMANDS_BIT or PIPELINE_STAGE_2_RAY_TRACING_SHADER_BIT_KHR
• If dstAccessMask includes VK_ACCESS_2_VIDEO_DECODE_READ_BIT_KHR, dstStageMask must include VK_PIPELINE_STAGE_2_VIDEO_DECODE_BIT_KHR
• If dstAccessMask includes VK_ACCESS_2_VIDEO_DECODE_WRITE_BIT_KHR, dstStageMask must include VK_PIPELINE_STAGE_2_VIDEO_DECODE_BIT_KHR
• If dstAccessMask includes VK_ACCESS_2_VIDEO_ENCODE_READ_BIT_KHR, dstStageMask must include VK_PIPELINE_STAGE_2_VIDEO_ENCODE_BIT_KHR
• If dstAccessMask includes VK_ACCESS_2_VIDEO_ENCODE_WRITE_BIT_KHR, dstStageMask must include VK_PIPELINE_STAGE_2_VIDEO_ENCODE_BIT_KHR
• If dstAccessMask includes ACCESS_2_OPTICAL_FLOW_READ_BIT_NV, dstStageMask must include PIPELINE_STAGE_2_OPTICAL_FLOW_BIT_NV
• If dstAccessMask includes ACCESS_2_OPTICAL_FLOW_WRITE_BIT_NV, dstStageMask must include PIPELINE_STAGE_2_OPTICAL_FLOW_BIT_NV
• If dstAccessMask includes ACCESS_2_MICROMAP_WRITE_BIT_EXT, dstStageMask must include PIPELINE_STAGE_2_MICROMAP_BUILD_BIT_EXT
• If dstAccessMask includes ACCESS_2_MICROMAP_READ_BIT_EXT, dstStageMask must include PIPELINE_STAGE_2_MICROMAP_BUILD_BIT_EXT or PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR
• If dstAccessMask includes ACCESS_2_DESCRIPTOR_BUFFER_READ_BIT_EXT, dstStageMask must include PIPELINE_STAGE_2_ALL_GRAPHICS_BIT, PIPELINE_STAGE_2_ALL_COMMANDS_BIT, or one of VK_PIPELINE_STAGE_*_SHADER_BIT stages
• If srcQueueFamilyIndex and dstQueueFamilyIndex define a queue family ownership transfer or oldLayout and newLayout define an image layout transition, and oldLayout or newLayout is IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL then image must have been created with IMAGE_USAGE_COLOR_ATTACHMENT_BIT
• If srcQueueFamilyIndex and dstQueueFamilyIndex define a queue family ownership transfer or oldLayout and newLayout define an image layout transition, and oldLayout or newLayout is IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL then image must have been created with IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
• If srcQueueFamilyIndex and dstQueueFamilyIndex define a queue family ownership transfer or oldLayout and newLayout define an image layout transition, and oldLayout or newLayout is IMAGE_LAYOUT_DEPTH_STENCIL_READ_ONLY_OPTIMAL then image must have been created with IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
• If srcQueueFamilyIndex and dstQueueFamilyIndex define a queue family ownership transfer or oldLayout and newLayout define an image layout transition, and oldLayout or newLayout is IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL then image must have been created with IMAGE_USAGE_SAMPLED_BIT or IMAGE_USAGE_INPUT_ATTACHMENT_BIT
• If srcQueueFamilyIndex and dstQueueFamilyIndex define a queue family ownership transfer or oldLayout and newLayout define an image layout transition, and oldLayout or newLayout is IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL then image must have been created with IMAGE_USAGE_TRANSFER_SRC_BIT
• If srcQueueFamilyIndex and dstQueueFamilyIndex define a queue family ownership transfer or oldLayout and newLayout define an image layout transition, and oldLayout or newLayout is IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL then image must have been created with IMAGE_USAGE_TRANSFER_DST_BIT
• If srcQueueFamilyIndex and dstQueueFamilyIndex define a queue family ownership transfer or oldLayout and newLayout define an image layout transition, oldLayout must be IMAGE_LAYOUT_UNDEFINED or the current layout of the image subresources affected by the barrier
• If srcQueueFamilyIndex and dstQueueFamilyIndex define a queue family ownership transfer or oldLayout and newLayout define an image layout transition, newLayout must not be IMAGE_LAYOUT_UNDEFINED or IMAGE_LAYOUT_PREINITIALIZED
• If srcQueueFamilyIndex and dstQueueFamilyIndex define a queue family ownership transfer or oldLayout and newLayout define an image layout transition, and oldLayout or newLayout is IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL then image must have been created with IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
• If srcQueueFamilyIndex and dstQueueFamilyIndex define a queue family ownership transfer or oldLayout and newLayout define an image layout transition, and oldLayout or newLayout is IMAGE_LAYOUT_DEPTH_ATTACHMENT_STENCIL_READ_ONLY_OPTIMAL then image must have been created with IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
• If srcQueueFamilyIndex and dstQueueFamilyIndex define a queue family ownership transfer or oldLayout and newLayout define an image layout transition, and oldLayout or newLayout is IMAGE_LAYOUT_DEPTH_READ_ONLY_OPTIMAL then image must have been created with at least one of IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT, IMAGE_USAGE_SAMPLED_BIT, or IMAGE_USAGE_INPUT_ATTACHMENT_BIT
• If srcQueueFamilyIndex and dstQueueFamilyIndex define a queue family ownership transfer or oldLayout and newLayout define an image layout transition, and oldLayout or newLayout is IMAGE_LAYOUT_DEPTH_ATTACHMENT_OPTIMAL then image must have been created with IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT set
• If srcQueueFamilyIndex and dstQueueFamilyIndex define a queue family ownership transfer or oldLayout and newLayout define an image layout transition, and oldLayout or newLayout is IMAGE_LAYOUT_STENCIL_READ_ONLY_OPTIMAL then image must have been created with at least one of IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT, IMAGE_USAGE_SAMPLED_BIT, or IMAGE_USAGE_INPUT_ATTACHMENT_BIT
• If srcQueueFamilyIndex and dstQueueFamilyIndex define a queue family ownership transfer or oldLayout and newLayout define an image layout transition, and oldLayout or newLayout is IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL then image must have been created with IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT set
• If the synchronization2 feature is not enabled, oldLayout must not be IMAGE_LAYOUT_ATTACHMENT_OPTIMAL_KHR or IMAGE_LAYOUT_READ_ONLY_OPTIMAL_KHR
• If the synchronization2 feature is not enabled, newLayout must not be IMAGE_LAYOUT_ATTACHMENT_OPTIMAL_KHR or IMAGE_LAYOUT_READ_ONLY_OPTIMAL_KHR
• If srcQueueFamilyIndex and dstQueueFamilyIndex define a queue family ownership transfer or oldLayout and newLayout define an image layout transition, and oldLayout or newLayout is IMAGE_LAYOUT_ATTACHMENT_OPTIMAL, image must have been created with IMAGE_USAGE_COLOR_ATTACHMENT_BIT or IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
• If srcQueueFamilyIndex and dstQueueFamilyIndex define a queue family ownership transfer or oldLayout and newLayout define an image layout transition, and oldLayout or newLayout is IMAGE_LAYOUT_READ_ONLY_OPTIMAL, image must have been created with at least one of IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT, IMAGE_USAGE_SAMPLED_BIT, or IMAGE_USAGE_INPUT_ATTACHMENT_BIT
• If srcQueueFamilyIndex and dstQueueFamilyIndex define a queue family ownership transfer or oldLayout and newLayout define an image layout transition, and oldLayout or newLayout is IMAGE_LAYOUT_FRAGMENT_SHADING_RATE_ATTACHMENT_OPTIMAL_KHR then image must have been created with IMAGE_USAGE_FRAGMENT_SHADING_RATE_ATTACHMENT_BIT_KHR set
• If image was created with a sharing mode of SHARING_MODE_EXCLUSIVE, and srcQueueFamilyIndex and dstQueueFamilyIndex are not equal, srcQueueFamilyIndex must be QUEUE_FAMILY_EXTERNAL, QUEUE_FAMILY_FOREIGN_EXT, or a valid queue family
• If image was created with a sharing mode of SHARING_MODE_EXCLUSIVE, and srcQueueFamilyIndex and dstQueueFamilyIndex are not equal, dstQueueFamilyIndex must be QUEUE_FAMILY_EXTERNAL, QUEUE_FAMILY_FOREIGN_EXT, or a valid queue family
• If srcQueueFamilyIndex is not equal to dstQueueFamilyIndex, at least one of srcQueueFamilyIndex or dstQueueFamilyIndex must not be QUEUE_FAMILY_EXTERNAL or QUEUE_FAMILY_FOREIGN_EXT
• If the VK_KHR_external_memory extension is not enabled, and the value of ApplicationInfo::apiVersion used to create the Instance is not greater than or equal to Version 1.1, srcQueueFamilyIndex must not be QUEUE_FAMILY_EXTERNAL
• If the VK_KHR_external_memory extension is not enabled, and the value of ApplicationInfo::apiVersion used to create the Instance is not greater than or equal to Version 1.1, dstQueueFamilyIndex must not be QUEUE_FAMILY_EXTERNAL
• If the VK_EXT_queue_family_foreign extension is not enabled srcQueueFamilyIndex must not be QUEUE_FAMILY_FOREIGN_EXT
• If the VK_EXT_queue_family_foreign extension is not enabled dstQueueFamilyIndex must not be QUEUE_FAMILY_FOREIGN_EXT
• If srcQueueFamilyIndex and dstQueueFamilyIndex define a queue family ownership transfer or oldLayout and newLayout define an image layout transition, and oldLayout or newLayout is VK_IMAGE_LAYOUT_VIDEO_DECODE_SRC_KHR then image must have been created with VK_IMAGE_USAGE_VIDEO_DECODE_SRC_BIT_KHR
• If srcQueueFamilyIndex and dstQueueFamilyIndex define a queue family ownership transfer or oldLayout and newLayout define an image layout transition, and oldLayout or newLayout is VK_IMAGE_LAYOUT_VIDEO_DECODE_DST_KHR then image must have been created with VK_IMAGE_USAGE_VIDEO_DECODE_DST_BIT_KHR
• If srcQueueFamilyIndex and dstQueueFamilyIndex define a queue family ownership transfer or oldLayout and newLayout define an image layout transition, and oldLayout or newLayout is VK_IMAGE_LAYOUT_VIDEO_DECODE_DPB_KHR then image must have been created with VK_IMAGE_USAGE_VIDEO_DECODE_DPB_BIT_KHR
• If srcQueueFamilyIndex and dstQueueFamilyIndex define a queue family ownership transfer or oldLayout and newLayout define an image layout transition, and oldLayout or newLayout is VK_IMAGE_LAYOUT_VIDEO_ENCODE_SRC_KHR then image must have been created with VK_IMAGE_USAGE_VIDEO_ENCODE_SRC_BIT_KHR
• If srcQueueFamilyIndex and dstQueueFamilyIndex define a queue family ownership transfer or oldLayout and newLayout define an image layout transition, and oldLayout or newLayout is VK_IMAGE_LAYOUT_VIDEO_ENCODE_DST_KHR then image must have been created with VK_IMAGE_USAGE_VIDEO_ENCODE_DST_BIT_KHR
• If srcQueueFamilyIndex and dstQueueFamilyIndex define a queue family ownership transfer or oldLayout and newLayout define an image layout transition, and oldLayout or newLayout is VK_IMAGE_LAYOUT_VIDEO_ENCODE_DPB_KHR then image must have been created with VK_IMAGE_USAGE_VIDEO_ENCODE_DPB_BIT_KHR
• If srcQueueFamilyIndex and dstQueueFamilyIndex define a queue family ownership transfer or oldLayout and newLayout define an image layout transition, and oldLayout or newLayout is IMAGE_LAYOUT_ATTACHMENT_FEEDBACK_LOOP_OPTIMAL_EXT then image must have been created with either the IMAGE_USAGE_COLOR_ATTACHMENT_BIT or IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT usage bits, and the IMAGE_USAGE_INPUT_ATTACHMENT_BIT or IMAGE_USAGE_SAMPLED_BIT usage bits, and the IMAGE_USAGE_ATTACHMENT_FEEDBACK_LOOP_BIT_EXT usage bit
• If the attachmentFeedbackLoopLayout feature is not enabled, newLayout must not be IMAGE_LAYOUT_ATTACHMENT_FEEDBACK_LOOP_OPTIMAL_EXT
• subresourceRange.baseMipLevel must be less than the mipLevels specified in ImageCreateInfo when image was created
• If subresourceRange.levelCount is not REMAINING_MIP_LEVELS, subresourceRange.baseMipLevel + subresourceRange.levelCount must be less than or equal to the mipLevels specified in ImageCreateInfo when image was created
• subresourceRange.baseArrayLayer must be less than the arrayLayers specified in ImageCreateInfo when image was created
• If subresourceRange.layerCount is not REMAINING_ARRAY_LAYERS, subresourceRange.baseArrayLayer + subresourceRange.layerCount must be less than or equal to the arrayLayers specified in ImageCreateInfo when image was created
• If image is non-sparse then it must be bound completely and contiguously to a single DeviceMemory object
• If image has a color format that is single-plane, then the aspectMask member of subresourceRange must be IMAGE_ASPECT_COLOR_BIT
• If image has a color format and is not disjoint, then the aspectMask member of subresourceRange must be IMAGE_ASPECT_COLOR_BIT
• If image has a multi-planar format and the image is disjoint, then the aspectMask member of subresourceRange must include at least one multi-planar aspect mask bit or IMAGE_ASPECT_COLOR_BIT
• If image has a depth/stencil format with both depth and stencil and the separateDepthStencilLayouts feature is enabled, then the aspectMask member of subresourceRange must include either or both IMAGE_ASPECT_DEPTH_BIT and IMAGE_ASPECT_STENCIL_BIT
• If image has a depth/stencil format with both depth and stencil and the separateDepthStencilLayouts feature is not enabled, then the aspectMask member of subresourceRange must include both IMAGE_ASPECT_DEPTH_BIT and IMAGE_ASPECT_STENCIL_BIT
• If the aspectMask member of subresourceRange includes IMAGE_ASPECT_DEPTH_BIT, oldLayout and newLayout must not be one of IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL or IMAGE_LAYOUT_STENCIL_READ_ONLY_OPTIMAL
• If the aspectMask member of subresourceRange includes IMAGE_ASPECT_STENCIL_BIT, oldLayout and newLayout must not be one of IMAGE_LAYOUT_DEPTH_ATTACHMENT_OPTIMAL or IMAGE_LAYOUT_DEPTH_READ_ONLY_OPTIMAL
• If either srcStageMask or dstStageMask includes PIPELINE_STAGE_2_HOST_BIT, srcQueueFamilyIndex and dstQueueFamilyIndex must be equal
• If srcStageMask includes PIPELINE_STAGE_2_HOST_BIT, and srcQueueFamilyIndex and dstQueueFamilyIndex define a queue family ownership transfer or oldLayout and newLayout define an image layout transition, oldLayout must be one of IMAGE_LAYOUT_PREINITIALIZED, IMAGE_LAYOUT_UNDEFINED, or IMAGE_LAYOUT_GENERAL