vulkan-3.26.1: Bindings to the Vulkan graphics API.
Safe HaskellSafe-Inferred
LanguageHaskell2010

Vulkan.Core10.Enums.AccessFlagBits

Synopsis

Documentation

newtype AccessFlagBits Source #

VkAccessFlagBits - Bitmask specifying memory access types that will participate in a memory dependency

Description

These values all have the same meaning as the equivalently named values for AccessFlags2.

Certain access types are only performed by a subset of pipeline stages. Any synchronization command that takes both stage masks and access masks uses both to define the access scopes - only the specified access types performed by the specified stages are included in the access scope. An application must not specify an access flag in a synchronization command if it does not include a pipeline stage in the corresponding stage mask that is able to perform accesses of that type. The following table lists, for each access flag, which pipeline stages can perform that type of access.

Access flagSupported pipeline stages
ACCESS_2_NONEAny
ACCESS_2_INDIRECT_COMMAND_READ_BIT PIPELINE_STAGE_2_DRAW_INDIRECT_BIT, PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR
ACCESS_2_INDEX_READ_BIT PIPELINE_STAGE_2_VERTEX_INPUT_BIT, PIPELINE_STAGE_2_INDEX_INPUT_BIT
ACCESS_2_VERTEX_ATTRIBUTE_READ_BIT PIPELINE_STAGE_2_VERTEX_INPUT_BIT, PIPELINE_STAGE_2_VERTEX_ATTRIBUTE_INPUT_BIT
ACCESS_2_UNIFORM_READ_BIT PIPELINE_STAGE_2_VERTEX_SHADER_BIT, PIPELINE_STAGE_2_TESSELLATION_CONTROL_SHADER_BIT, PIPELINE_STAGE_2_TESSELLATION_EVALUATION_SHADER_BIT, PIPELINE_STAGE_2_GEOMETRY_SHADER_BIT, PIPELINE_STAGE_2_FRAGMENT_SHADER_BIT, PIPELINE_STAGE_2_COMPUTE_SHADER_BIT, PIPELINE_STAGE_2_RAY_TRACING_SHADER_BIT_KHR, PIPELINE_STAGE_2_TASK_SHADER_BIT_EXT, PIPELINE_STAGE_2_MESH_SHADER_BIT_EXT, PIPELINE_STAGE_2_SUBPASS_SHADER_BIT_HUAWEI, PIPELINE_STAGE_2_CLUSTER_CULLING_SHADER_BIT_HUAWEI
ACCESS_2_INPUT_ATTACHMENT_READ_BIT PIPELINE_STAGE_2_FRAGMENT_SHADER_BIT, PIPELINE_STAGE_2_SUBPASS_SHADER_BIT_HUAWEI
ACCESS_2_SHADER_READ_BIT PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR, PIPELINE_STAGE_2_MICROMAP_BUILD_BIT_EXT, PIPELINE_STAGE_2_VERTEX_SHADER_BIT, PIPELINE_STAGE_2_TESSELLATION_CONTROL_SHADER_BIT, PIPELINE_STAGE_2_TESSELLATION_EVALUATION_SHADER_BIT, PIPELINE_STAGE_2_GEOMETRY_SHADER_BIT, PIPELINE_STAGE_2_FRAGMENT_SHADER_BIT, PIPELINE_STAGE_2_COMPUTE_SHADER_BIT, PIPELINE_STAGE_2_RAY_TRACING_SHADER_BIT_KHR, PIPELINE_STAGE_2_TASK_SHADER_BIT_EXT, PIPELINE_STAGE_2_MESH_SHADER_BIT_EXT, PIPELINE_STAGE_2_SUBPASS_SHADER_BIT_HUAWEI, PIPELINE_STAGE_2_CLUSTER_CULLING_SHADER_BIT_HUAWEI
ACCESS_2_SHADER_WRITE_BIT PIPELINE_STAGE_2_VERTEX_SHADER_BIT, PIPELINE_STAGE_2_TESSELLATION_CONTROL_SHADER_BIT, PIPELINE_STAGE_2_TESSELLATION_EVALUATION_SHADER_BIT, PIPELINE_STAGE_2_GEOMETRY_SHADER_BIT, PIPELINE_STAGE_2_FRAGMENT_SHADER_BIT, PIPELINE_STAGE_2_COMPUTE_SHADER_BIT, PIPELINE_STAGE_2_RAY_TRACING_SHADER_BIT_KHR, PIPELINE_STAGE_2_TASK_SHADER_BIT_EXT, PIPELINE_STAGE_2_MESH_SHADER_BIT_EXT, PIPELINE_STAGE_2_SUBPASS_SHADER_BIT_HUAWEI, PIPELINE_STAGE_2_CLUSTER_CULLING_SHADER_BIT_HUAWEI
ACCESS_2_COLOR_ATTACHMENT_READ_BIT PIPELINE_STAGE_2_FRAGMENT_SHADER_BIT, PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT
ACCESS_2_COLOR_ATTACHMENT_WRITE_BITPIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT
ACCESS_2_DEPTH_STENCIL_ATTACHMENT_READ_BIT PIPELINE_STAGE_2_FRAGMENT_SHADER_BIT, PIPELINE_STAGE_2_EARLY_FRAGMENT_TESTS_BIT, PIPELINE_STAGE_2_LATE_FRAGMENT_TESTS_BIT
ACCESS_2_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT PIPELINE_STAGE_2_EARLY_FRAGMENT_TESTS_BIT, PIPELINE_STAGE_2_LATE_FRAGMENT_TESTS_BIT
ACCESS_2_TRANSFER_READ_BIT PIPELINE_STAGE_2_ALL_TRANSFER_BIT, PIPELINE_STAGE_2_COPY_BIT, PIPELINE_STAGE_2_RESOLVE_BIT, PIPELINE_STAGE_2_BLIT_BIT, PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR, PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_COPY_BIT_KHR, PIPELINE_STAGE_2_MICROMAP_BUILD_BIT_EXT
ACCESS_2_TRANSFER_WRITE_BIT PIPELINE_STAGE_2_ALL_TRANSFER_BIT, PIPELINE_STAGE_2_COPY_BIT, PIPELINE_STAGE_2_RESOLVE_BIT, PIPELINE_STAGE_2_BLIT_BIT, PIPELINE_STAGE_2_CLEAR_BIT, PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR, PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_COPY_BIT_KHR, PIPELINE_STAGE_2_MICROMAP_BUILD_BIT_EXT
ACCESS_2_HOST_READ_BITPIPELINE_STAGE_2_HOST_BIT
ACCESS_2_HOST_WRITE_BITPIPELINE_STAGE_2_HOST_BIT
ACCESS_2_MEMORY_READ_BITAny
ACCESS_2_MEMORY_WRITE_BITAny
ACCESS_2_SHADER_SAMPLED_READ_BIT PIPELINE_STAGE_2_VERTEX_SHADER_BIT, PIPELINE_STAGE_2_TESSELLATION_CONTROL_SHADER_BIT, PIPELINE_STAGE_2_TESSELLATION_EVALUATION_SHADER_BIT, PIPELINE_STAGE_2_GEOMETRY_SHADER_BIT, PIPELINE_STAGE_2_FRAGMENT_SHADER_BIT, PIPELINE_STAGE_2_COMPUTE_SHADER_BIT, PIPELINE_STAGE_2_RAY_TRACING_SHADER_BIT_KHR, PIPELINE_STAGE_2_TASK_SHADER_BIT_EXT, PIPELINE_STAGE_2_MESH_SHADER_BIT_EXT, PIPELINE_STAGE_2_SUBPASS_SHADER_BIT_HUAWEI, PIPELINE_STAGE_2_CLUSTER_CULLING_SHADER_BIT_HUAWEI
ACCESS_2_SHADER_STORAGE_READ_BIT PIPELINE_STAGE_2_VERTEX_SHADER_BIT, PIPELINE_STAGE_2_TESSELLATION_CONTROL_SHADER_BIT, PIPELINE_STAGE_2_TESSELLATION_EVALUATION_SHADER_BIT, PIPELINE_STAGE_2_GEOMETRY_SHADER_BIT, PIPELINE_STAGE_2_FRAGMENT_SHADER_BIT, PIPELINE_STAGE_2_COMPUTE_SHADER_BIT, PIPELINE_STAGE_2_RAY_TRACING_SHADER_BIT_KHR, PIPELINE_STAGE_2_TASK_SHADER_BIT_EXT, PIPELINE_STAGE_2_MESH_SHADER_BIT_EXT, PIPELINE_STAGE_2_SUBPASS_SHADER_BIT_HUAWEI, PIPELINE_STAGE_2_CLUSTER_CULLING_SHADER_BIT_HUAWEI
ACCESS_2_SHADER_STORAGE_WRITE_BIT PIPELINE_STAGE_2_VERTEX_SHADER_BIT, PIPELINE_STAGE_2_TESSELLATION_CONTROL_SHADER_BIT, PIPELINE_STAGE_2_TESSELLATION_EVALUATION_SHADER_BIT, PIPELINE_STAGE_2_GEOMETRY_SHADER_BIT, PIPELINE_STAGE_2_FRAGMENT_SHADER_BIT, PIPELINE_STAGE_2_COMPUTE_SHADER_BIT, PIPELINE_STAGE_2_RAY_TRACING_SHADER_BIT_KHR, PIPELINE_STAGE_2_TASK_SHADER_BIT_EXT, PIPELINE_STAGE_2_MESH_SHADER_BIT_EXT, PIPELINE_STAGE_2_SUBPASS_SHADER_BIT_HUAWEI, PIPELINE_STAGE_2_CLUSTER_CULLING_SHADER_BIT_HUAWEI
VK_ACCESS_2_VIDEO_DECODE_READ_BIT_KHRVK_PIPELINE_STAGE_2_VIDEO_DECODE_BIT_KHR
VK_ACCESS_2_VIDEO_DECODE_WRITE_BIT_KHRVK_PIPELINE_STAGE_2_VIDEO_DECODE_BIT_KHR
VK_ACCESS_2_VIDEO_ENCODE_READ_BIT_KHRVK_PIPELINE_STAGE_2_VIDEO_ENCODE_BIT_KHR
VK_ACCESS_2_VIDEO_ENCODE_WRITE_BIT_KHRVK_PIPELINE_STAGE_2_VIDEO_ENCODE_BIT_KHR
ACCESS_2_TRANSFORM_FEEDBACK_WRITE_BIT_EXTPIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT
ACCESS_2_TRANSFORM_FEEDBACK_COUNTER_READ_BIT_EXT PIPELINE_STAGE_2_DRAW_INDIRECT_BIT, PIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT
ACCESS_2_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXTPIPELINE_STAGE_2_TRANSFORM_FEEDBACK_BIT_EXT
ACCESS_2_CONDITIONAL_RENDERING_READ_BIT_EXTPIPELINE_STAGE_2_CONDITIONAL_RENDERING_BIT_EXT
ACCESS_2_COMMAND_PREPROCESS_READ_BIT_NVPIPELINE_STAGE_2_COMMAND_PREPROCESS_BIT_NV
ACCESS_2_COMMAND_PREPROCESS_WRITE_BIT_NVPIPELINE_STAGE_2_COMMAND_PREPROCESS_BIT_NV
ACCESS_2_FRAGMENT_SHADING_RATE_ATTACHMENT_READ_BIT_KHRPIPELINE_STAGE_2_FRAGMENT_SHADING_RATE_ATTACHMENT_BIT_KHR
ACCESS_2_ACCELERATION_STRUCTURE_READ_BIT_KHR PIPELINE_STAGE_2_VERTEX_SHADER_BIT, PIPELINE_STAGE_2_TESSELLATION_CONTROL_SHADER_BIT, PIPELINE_STAGE_2_TESSELLATION_EVALUATION_SHADER_BIT, PIPELINE_STAGE_2_GEOMETRY_SHADER_BIT, PIPELINE_STAGE_2_FRAGMENT_SHADER_BIT, PIPELINE_STAGE_2_COMPUTE_SHADER_BIT, PIPELINE_STAGE_2_RAY_TRACING_SHADER_BIT_KHR, PIPELINE_STAGE_2_TASK_SHADER_BIT_EXT, PIPELINE_STAGE_2_MESH_SHADER_BIT_EXT, PIPELINE_STAGE_2_CLUSTER_CULLING_SHADER_BIT_HUAWEI, PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR, PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_COPY_BIT_KHR, PIPELINE_STAGE_2_SUBPASS_SHADER_BIT_HUAWEI
ACCESS_2_ACCELERATION_STRUCTURE_WRITE_BIT_KHR PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR, PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_COPY_BIT_KHR
ACCESS_2_FRAGMENT_DENSITY_MAP_READ_BIT_EXTPIPELINE_STAGE_2_FRAGMENT_DENSITY_PROCESS_BIT_EXT
ACCESS_2_COLOR_ATTACHMENT_READ_NONCOHERENT_BIT_EXTPIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT
ACCESS_2_DESCRIPTOR_BUFFER_READ_BIT_EXT PIPELINE_STAGE_2_VERTEX_SHADER_BIT, PIPELINE_STAGE_2_TESSELLATION_CONTROL_SHADER_BIT, PIPELINE_STAGE_2_TESSELLATION_EVALUATION_SHADER_BIT, PIPELINE_STAGE_2_GEOMETRY_SHADER_BIT, PIPELINE_STAGE_2_FRAGMENT_SHADER_BIT, PIPELINE_STAGE_2_COMPUTE_SHADER_BIT, PIPELINE_STAGE_2_RAY_TRACING_SHADER_BIT_KHR, PIPELINE_STAGE_2_TASK_SHADER_BIT_EXT, PIPELINE_STAGE_2_MESH_SHADER_BIT_EXT, PIPELINE_STAGE_2_SUBPASS_SHADER_BIT_HUAWEI, PIPELINE_STAGE_2_CLUSTER_CULLING_SHADER_BIT_HUAWEI
ACCESS_2_INVOCATION_MASK_READ_BIT_HUAWEIPIPELINE_STAGE_2_INVOCATION_MASK_BIT_HUAWEI
ACCESS_2_SHADER_BINDING_TABLE_READ_BIT_KHR PIPELINE_STAGE_2_VERTEX_SHADER_BIT, PIPELINE_STAGE_2_TESSELLATION_CONTROL_SHADER_BIT, PIPELINE_STAGE_2_TESSELLATION_EVALUATION_SHADER_BIT, PIPELINE_STAGE_2_GEOMETRY_SHADER_BIT, PIPELINE_STAGE_2_FRAGMENT_SHADER_BIT, PIPELINE_STAGE_2_COMPUTE_SHADER_BIT, PIPELINE_STAGE_2_RAY_TRACING_SHADER_BIT_KHR, PIPELINE_STAGE_2_TASK_SHADER_BIT_EXT, PIPELINE_STAGE_2_MESH_SHADER_BIT_EXT, PIPELINE_STAGE_2_SUBPASS_SHADER_BIT_HUAWEI, PIPELINE_STAGE_2_CLUSTER_CULLING_SHADER_BIT_HUAWEI
ACCESS_2_MICROMAP_READ_BIT_EXT PIPELINE_STAGE_2_MICROMAP_BUILD_BIT_EXT, PIPELINE_STAGE_2_ACCELERATION_STRUCTURE_BUILD_BIT_KHR
ACCESS_2_MICROMAP_WRITE_BIT_EXTPIPELINE_STAGE_2_MICROMAP_BUILD_BIT_EXT
ACCESS_2_OPTICAL_FLOW_READ_BIT_NVPIPELINE_STAGE_2_OPTICAL_FLOW_BIT_NV
ACCESS_2_OPTICAL_FLOW_WRITE_BIT_NVPIPELINE_STAGE_2_OPTICAL_FLOW_BIT_NV

Supported access types

See Also

VK_VERSION_1_0, AccessFlags

Constructors

AccessFlagBits Flags 

Bundled Patterns

pattern ACCESS_INDIRECT_COMMAND_READ_BIT :: AccessFlagBits

ACCESS_INDIRECT_COMMAND_READ_BIT specifies read access to indirect command data read as part of an indirect build, trace, drawing or dispatching command. Such access occurs in the PIPELINE_STAGE_DRAW_INDIRECT_BIT pipeline stage.

pattern ACCESS_INDEX_READ_BIT :: AccessFlagBits

ACCESS_INDEX_READ_BIT specifies read access to an index buffer as part of an indexed drawing command, bound by cmdBindIndexBuffer2KHR and cmdBindIndexBuffer. Such access occurs in the PIPELINE_STAGE_VERTEX_INPUT_BIT pipeline stage.

pattern ACCESS_VERTEX_ATTRIBUTE_READ_BIT :: AccessFlagBits

ACCESS_VERTEX_ATTRIBUTE_READ_BIT specifies read access to a vertex buffer as part of a drawing command, bound by cmdBindVertexBuffers. Such access occurs in the PIPELINE_STAGE_VERTEX_INPUT_BIT pipeline stage.

pattern ACCESS_UNIFORM_READ_BIT :: AccessFlagBits

ACCESS_UNIFORM_READ_BIT specifies read access to a uniform buffer in any shader pipeline stage.

pattern ACCESS_INPUT_ATTACHMENT_READ_BIT :: AccessFlagBits

ACCESS_INPUT_ATTACHMENT_READ_BIT specifies read access to an input attachment within a render pass during subpass shading or fragment shading. Such access occurs in the PIPELINE_STAGE_2_SUBPASS_SHADER_BIT_HUAWEI or PIPELINE_STAGE_FRAGMENT_SHADER_BIT pipeline stage.

pattern ACCESS_SHADER_READ_BIT :: AccessFlagBits

ACCESS_SHADER_READ_BIT specifies read access to a uniform texel buffer, sampled image, storage buffer, physical storage buffer, shader binding table, storage texel buffer, or storage image in any shader pipeline stage.

pattern ACCESS_SHADER_WRITE_BIT :: AccessFlagBits

ACCESS_SHADER_WRITE_BIT specifies write access to a storage buffer, physical storage buffer, storage texel buffer, or storage image in any shader pipeline stage.

pattern ACCESS_COLOR_ATTACHMENT_READ_BIT :: AccessFlagBits

ACCESS_COLOR_ATTACHMENT_READ_BIT specifies read access to a color attachment, such as via blending (other than advanced blend operations), logic operations or certain render pass load operations in the PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT pipeline stage or via fragment shader tile image reads in the PIPELINE_STAGE_FRAGMENT_SHADER_BIT pipeline stage.

pattern ACCESS_COLOR_ATTACHMENT_WRITE_BIT :: AccessFlagBits

ACCESS_COLOR_ATTACHMENT_WRITE_BIT specifies write access to a color, resolve, or depth/stencil resolve attachment during a render pass or via certain render pass load and store operations. Such access occurs in the PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT pipeline stage.

pattern ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT :: AccessFlagBits

ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT specifies read access to a depth/stencil attachment, via depth or stencil operations or certain render pass load operations in the PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT or PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT pipeline stages or via fragment shader tile image reads in the PIPELINE_STAGE_FRAGMENT_SHADER_BIT pipeline stage.

pattern ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT :: AccessFlagBits

ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT specifies write access to a depth/stencil attachment, via depth or stencil operations or certain render pass load and store operations. Such access occurs in the PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT or PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT pipeline stages.

pattern ACCESS_TRANSFER_READ_BIT :: AccessFlagBits

ACCESS_TRANSFER_READ_BIT specifies read access to an image or buffer in a copy operation. Such access occurs in the PIPELINE_STAGE_2_ALL_TRANSFER_BIT pipeline stage.

pattern ACCESS_TRANSFER_WRITE_BIT :: AccessFlagBits

ACCESS_TRANSFER_WRITE_BIT specifies write access to an image or buffer in a clear or copy operation. Such access occurs in the PIPELINE_STAGE_2_ALL_TRANSFER_BIT pipeline stage.

pattern ACCESS_HOST_READ_BIT :: AccessFlagBits

ACCESS_HOST_READ_BIT specifies read access by a host operation. Accesses of this type are not performed through a resource, but directly on memory. Such access occurs in the PIPELINE_STAGE_HOST_BIT pipeline stage.

pattern ACCESS_HOST_WRITE_BIT :: AccessFlagBits

ACCESS_HOST_WRITE_BIT specifies write access by a host operation. Accesses of this type are not performed through a resource, but directly on memory. Such access occurs in the PIPELINE_STAGE_HOST_BIT pipeline stage.

pattern ACCESS_MEMORY_READ_BIT :: AccessFlagBits

ACCESS_MEMORY_READ_BIT specifies all read accesses. It is always valid in any access mask, and is treated as equivalent to setting all READ access flags that are valid where it is used.

pattern ACCESS_MEMORY_WRITE_BIT :: AccessFlagBits

ACCESS_MEMORY_WRITE_BIT specifies all write accesses. It is always valid in any access mask, and is treated as equivalent to setting all WRITE access flags that are valid where it is used.

pattern ACCESS_COMMAND_PREPROCESS_WRITE_BIT_NV :: AccessFlagBits

ACCESS_COMMAND_PREPROCESS_WRITE_BIT_NV specifies writes to the target command buffer preprocess outputs in cmdPreprocessGeneratedCommandsNV. Such access occurs in the PIPELINE_STAGE_COMMAND_PREPROCESS_BIT_NV pipeline stage.

pattern ACCESS_COMMAND_PREPROCESS_READ_BIT_NV :: AccessFlagBits

ACCESS_COMMAND_PREPROCESS_READ_BIT_NV specifies reads from buffer inputs to cmdPreprocessGeneratedCommandsNV. Such access occurs in the PIPELINE_STAGE_COMMAND_PREPROCESS_BIT_NV pipeline stage.

pattern ACCESS_FRAGMENT_SHADING_RATE_ATTACHMENT_READ_BIT_KHR :: AccessFlagBits

ACCESS_FRAGMENT_SHADING_RATE_ATTACHMENT_READ_BIT_KHR specifies read access to a fragment shading rate attachment during rasterization. Such access occurs in the PIPELINE_STAGE_FRAGMENT_SHADING_RATE_ATTACHMENT_BIT_KHR pipeline stage.

pattern ACCESS_FRAGMENT_DENSITY_MAP_READ_BIT_EXT :: AccessFlagBits

ACCESS_FRAGMENT_DENSITY_MAP_READ_BIT_EXT specifies read access to a fragment density map attachment during dynamic fragment density map operations Such access occurs in the PIPELINE_STAGE_FRAGMENT_DENSITY_PROCESS_BIT_EXT pipeline stage.

pattern ACCESS_ACCELERATION_STRUCTURE_WRITE_BIT_KHR :: AccessFlagBits

ACCESS_ACCELERATION_STRUCTURE_WRITE_BIT_KHR specifies write access to an acceleration structure or acceleration structure scratch buffer as part of a build or copy command. Such access occurs in the PIPELINE_STAGE_ACCELERATION_STRUCTURE_BUILD_BIT_KHR pipeline stage.

pattern ACCESS_ACCELERATION_STRUCTURE_READ_BIT_KHR :: AccessFlagBits

ACCESS_ACCELERATION_STRUCTURE_READ_BIT_KHR specifies read access to an acceleration structure as part of a trace, build, or copy command, or to an acceleration structure scratch buffer as part of a build command. Such access occurs in the PIPELINE_STAGE_RAY_TRACING_SHADER_BIT_KHR pipeline stage or PIPELINE_STAGE_ACCELERATION_STRUCTURE_BUILD_BIT_KHR pipeline stage.

pattern ACCESS_COLOR_ATTACHMENT_READ_NONCOHERENT_BIT_EXT :: AccessFlagBits

ACCESS_COLOR_ATTACHMENT_READ_NONCOHERENT_BIT_EXT specifies read access to color attachments, including advanced blend operations. Such access occurs in the PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT pipeline stage.

pattern ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT :: AccessFlagBits

ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT specifies read access to a predicate as part of conditional rendering. Such access occurs in the PIPELINE_STAGE_CONDITIONAL_RENDERING_BIT_EXT pipeline stage.

pattern ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT :: AccessFlagBits

ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT specifies write access to a transform feedback counter buffer which is written when cmdEndTransformFeedbackEXT executes. Such access occurs in the PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT pipeline stage.

pattern ACCESS_TRANSFORM_FEEDBACK_COUNTER_READ_BIT_EXT :: AccessFlagBits

ACCESS_TRANSFORM_FEEDBACK_COUNTER_READ_BIT_EXT specifies read access to a transform feedback counter buffer which is read when cmdBeginTransformFeedbackEXT executes. Such access occurs in the PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT pipeline stage.

pattern ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT :: AccessFlagBits

ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT specifies write access to a transform feedback buffer made when transform feedback is active. Such access occurs in the PIPELINE_STAGE_TRANSFORM_FEEDBACK_BIT_EXT pipeline stage.

pattern ACCESS_NONE :: AccessFlagBits

ACCESS_NONE specifies no accesses.

Instances

Instances details
Storable AccessFlagBits Source # 
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Defined in Vulkan.Core10.Enums.AccessFlagBits

Bits AccessFlagBits Source # 
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Defined in Vulkan.Core10.Enums.AccessFlagBits

FiniteBits AccessFlagBits Source # 
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Defined in Vulkan.Core10.Enums.AccessFlagBits

Read AccessFlagBits Source # 
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Defined in Vulkan.Core10.Enums.AccessFlagBits

Show AccessFlagBits Source # 
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Defined in Vulkan.Core10.Enums.AccessFlagBits

Eq AccessFlagBits Source # 
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Defined in Vulkan.Core10.Enums.AccessFlagBits

Ord AccessFlagBits Source # 
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Defined in Vulkan.Core10.Enums.AccessFlagBits

Zero AccessFlagBits Source # 
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Defined in Vulkan.Core10.Enums.AccessFlagBits