clash-lib: CAES Language for Synchronous Hardware - As a Library

[ bsd2, hardware, library, program ] [ Propose Tags ]

CλaSH (pronounced ‘clash’) is a functional hardware description language that borrows both its syntax and semantics from the functional programming language Haskell. The CλaSH compiler transforms these high-level descriptions to low-level synthesizable VHDL, Verilog, or SystemVerilog.

Features of CλaSH:

  • Strongly typed (like VHDL), yet with a very high degree of type inference, enabling both safe and fast prototying using consise descriptions (like Verilog).

  • Interactive REPL: load your designs in an interpreter and easily test all your component without needing to setup a test bench.

  • Higher-order functions, with type inference, result in designs that are fully parametric by default.

  • Synchronous sequential circuit design based on streams of values, called Signals, lead to natural descriptions of feedback loops.

  • Support for multiple clock domains, with type safe clock domain crossing.

This package provides:

  • The CoreHW internal language: SystemF + Letrec + Case-decomposition

  • The normalisation process that brings CoreHW in a normal form that can be converted to a netlist

  • Blackbox/Primitive Handling

Front-ends (for: parsing, typecheck, etc.) are provided by separate packages:

Prelude library: http://hackage.haskell.org/package/clash-prelude


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Versions [RSS] 0.2, 0.2.0.1, 0.2.1, 0.2.2, 0.2.2.1, 0.3, 0.3.0.1, 0.3.0.2, 0.3.0.3, 0.3.0.4, 0.3.1, 0.3.2, 0.4, 0.4.1, 0.5, 0.5.1, 0.5.2, 0.5.3, 0.5.4, 0.5.5, 0.5.6, 0.5.7, 0.5.8, 0.5.9, 0.5.10, 0.5.11, 0.5.12, 0.5.13, 0.6, 0.6.1, 0.6.2, 0.6.3, 0.6.4, 0.6.5, 0.6.6, 0.6.7, 0.6.8, 0.6.9, 0.6.10, 0.6.11, 0.6.12, 0.6.13, 0.6.14, 0.6.15, 0.6.16, 0.6.17, 0.6.18, 0.6.19, 0.6.20, 0.6.21, 0.7, 0.7.1, 0.99, 0.99.1, 0.99.2, 0.99.3, 1.0.0, 1.0.1, 1.2.0, 1.2.1, 1.2.2, 1.2.3, 1.2.4, 1.2.5, 1.4.0, 1.4.1, 1.4.2, 1.4.3, 1.4.4, 1.4.5, 1.4.6, 1.4.7, 1.6.0, 1.6.1, 1.6.2, 1.6.3, 1.6.4, 1.6.5, 1.6.6, 1.8.0, 1.8.1 (info)
Change log CHANGELOG.md
Dependencies aeson (>=0.6.2.0), attoparsec (>=0.10.4.0), base (>=4.8 && <5), bytestring (>=0.10.0.2), clash-prelude (>=0.10), concurrent-supply (>=0.1.7), containers (>=0.5.0.0), deepseq (>=1.3.0.2), directory (>=1.2.0.1), errors (>=1.4.2), fgl (>=5.4.2.4), filepath (>=1.3.0.1), hashable (>=1.2.1.0), lens (>=3.9.2), mtl (>=2.1.2), pretty (>=1.1.1.0), process (>=1.1.0.2), template-haskell (>=2.8.0.0), text (>=0.11.3.1), time (>=1.4.0.1), transformers (>=0.3.0.0), unbound-generics (>=0.1 && <0.3), unordered-containers (>=0.2.3.3), uu-parsinglib (>=2.8.1), wl-pprint-text (>=1.1.0.0) [details]
License BSD-2-Clause
Copyright Copyright © 2012-2015 University of Twente
Author Christiaan Baaij
Maintainer Christiaan Baaij <christiaan.baaij@gmail.com>
Category Hardware
Home page http://www.clash-lang.org/
Bug tracker http://github.com/clash-lang/clash-compiler/issues
Source repo head: git clone https://github.com/clash-lang/clash-compiler.git
Uploaded by ChristiaanBaaij at 2015-11-12T12:22:58Z
Distributions Arch:1.8.1, Stackage:1.8.1
Reverse Dependencies 10 direct, 0 indirect [details]
Downloads 59403 total (112 in the last 30 days)
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Status Docs available [build log]
Last success reported on 2015-12-04 [all 1 reports]

Readme for clash-lib-0.6.4

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clash-lib - CλaSH compiler, as a library

  • See the LICENSE file for license and copyright details

CλaSH - A functional hardware description language

CλaSH (pronounced ‘clash’) is a functional hardware description language that borrows both its syntax and semantics from the functional programming language Haskell. The CλaSH compiler transforms these high-level descriptions to low-level synthesizable VHDL, Verilog, or SystemVerilog.

Features of CλaSH:

  • Strongly typed (like VHDL), yet with a very high degree of type inference, enabling both safe and fast prototying using consise descriptions (like Verilog).

  • Interactive REPL: load your designs in an interpreter and easily test all your component without needing to setup a test bench.

  • Higher-order functions, with type inference, result in designs that are fully parametric by default.

  • Synchronous sequential circuit design based on streams of values, called Signals, lead to natural descriptions of feedback loops.

  • Support for multiple clock domains, with type safe clock domain crossing.

Support

For updates and questions join the mailing list clash-language+subscribe@googlegroups.com or read the forum