The Fabric structure, which is also a monad.

fabric_example :: Fabric ()
fabric_example = do
       i0 <- inStdLogic "i0"
       i1 <- inStdLogic "i1"
       let (c,s) = halfAdder i0 i1
       outStdLogic "carry" c
       outStdLogic "sum" s
 where
         halfAdder :: Seq Bool -> Seq Bool -> (Seq Bool,Seq Bool)
         halfAdder a b = (carry,sum_)
               where carry = and2 a b
                     sum_  = xor2 a b

A Fabric consists of a list of input ports, and yields a list of output ports and generics.

reifyFabric does reification of a 'Fabric ()' into a KLEG.

Generate a named std_logic input port.

Generate a named std_logic_vector port input.

Generate a named generic.

Generate a named std_logic output port, given a Lava circuit.

Generate a named std_logic_vector output port, given a Lava circuit.

theClk gives the external name for the clock.

theRst gives the external name for the reset signal [default = low].

theClkEn gives the external name for the clock enable signal [default = high].

These are sequences of values over time. We assume edge triggered logic (checked at (typically) rising edge of clock) This clock is assumed known, based on who is consuming the list. Right now, it is global, but we think we can support multiple clocks with a bit of work.

Signal in some implicit clock domain.

Convert a list of values into a Signal. The shallow portion of the resulting Signal will begin with the input list, then an infinite stream of X unknowns.

Convert a list of values into a Signal. The input list is wrapped with a Maybe, and any Nothing elements are mapped to X's unknowns.

Create a Signal with undefined for both the deep and shallow elements.

Convert a Signal of values into a list of Maybe values.

take the first n elements of a Signal; the rest is undefined.

A pure Signal.

A Signal witness identity function. Useful when typing things.

Attach a comment to a Signal.

Push the sign type *into* the compound data type.

A register is a state element with a reset. The reset is supplied by the clock domain in the Signal.

registers generates a serial sequence of n registers, all with the same initial value.

a delay is a register with no defined default / initial value.

delays generates a serial sequence of n delays.

The writeDotCircuit function converts a Lava circuit into a graphviz output.

Data structure for passing optimization parameters.

Basic optimizations, and assumes reaching a fixpoint. Cleans things up, but does not work too hard, because the VHDL compiler get many of the combinatorial optimizations anyway.

The vhdlCircuit function converts a Lava KLEG into a VHDL entity/architecture pair.

Write the Lava Prelude into this file. For example:

writeVhdlPrelude "Lava.vhd" 

VCD is a primary bit-wise record of an interactive session with some circuit Map from module/name to stream.

Convert a VCD to a VCD file.

Convert a VCD file to a VCD object.