Documentation

Enabled is a synonym for Maybe.

Combine a boolean control signal and an data signal into an enabled signal.

Break the representation of an Enabled signal into a Bool signal (for whether the value is valid) and a signal for the data.

Drop the Enabled control from the signal. The output signal will be Rep unknown if the input signal is not enabled.

Determine if the the circuit is enabled.

This is lifting *Comb* because Comb is stateless, and the en Bool being passed on assumes no history, in the 'a -> b' function.

Lift a data signal to be an Enabled signal, that's always enabled.

Create a signal that's never enabled.

Optionally updatable register, based on the value of the enabled signal.

A Pipe combines an address, data, and an Enabled control line.

A Memory takes in a sequence of addresses, and returns a sequence of data at that address.

Write the input pipe to memory, return a circuit that does reads.

Read a series of addresses. Respects the latency of Xilinx BRAMs.

Read a series of addresses.

memoryToMatrix should be used with caution/simulation only, because this actually clones the memory to allow this to work, generating lots of LUTs and BRAMS.

Apply a function to the Enabled input signal producing a Pipe.

Generate a read-only memory.

Take a list of shallow values and create a stream which can be sent into a FIFO, respecting the write-ready flag that comes out of the FIFO.

An AckBox producer that will go through a series of wait states after each time it drives the data output.

Take stream from a FIFO and return an asynchronous read-ready flag, which is given back to the FIFO, and a shallow list of values. I'm sure this space-leaks.

An ackBox that goes through a series of intermediate states each time consumes a value from the input stream and then issues an Ack.

enableToAckBox turns an Enabled signal into a (1-sided) Patch.

ackBoxToEnabled turns the AckBox protocol into the Enabled protocol. The assumptions is the circuit on the right is fast enough to handle the streamed data.

This introduces protocol-compliant delays (in the shallow embedding)

probeAckBoxPatch creates a patch with a named probe, probing the data and ack signals in an Ack interface.

A sink patch throws away its data input (generating a () data output). sinkReadyP uses an enabled/ack protocol.

A source patch takes no input and generates a stream of values. It corresponds to a top-level input port. sourceReadyP uses the enabled/ack protocol.

stub, no data ever sent.

Take a list of shallow values and create a stream which can be sent into a FIFO, respecting the write-ready flag that comes out of the FIFO.

A readybox that goes through a sequence of intermediate states after issuing each enable, and before it looks for the next Ready.

Take stream from a FIFO and return an asynchronous read-ready flag, which is given back to the FIFO, and a shallow list of values. I'm sure this space-leaks.

Like fromReadyBox, but which goes through a series of intermediate states after receiving an enable before issuing another Ready.

Introduces protocol-compliant delays (in the shallow embedding)

probeReadyBoxPatch creates a patch with a named probe, probing the data and ready signals in a Ready interface.

A sink patch throws away its data input (generating a () data output). sinkReadyP uses an enabled/ready protocol.

A source patch takes no input and generates a stream of values. It corresponds to a top-level input port. alwaysReadyP uses the ready/enabled protocol.

stub, no data ever sent.

An Ack is always in response to an incoming packet or message.

Convert a Bool signal to an Ack signal.

Convert an Ack to a Bool signal.

An Ready is always in response to an incoming packet or message

Convert a Bool signal to a Ready signal.

Convert a Ready signal to a Bool signal.

A Patch is a data signal with an associated control signal. The lhs_in type parameter is the type of the data input, the rhs_out type parameter is the type of the data output. The rhs_in is the type of the control input (e.g. a ready signal), and the lhs_out is the type of the control output (e.g. ack).

outputP produces a constant data output. The control inputs/outputs are unit, so they contain no data.

A patch that passes through data and control.

Given a patch, add to the data and control inputs/outputs a second set of signals that are passed-through. The signals of the argument patch to fstP will appear as the first element of the pair in the resulting patch.

Given a patch, add to the data and control inputs/outputs a second set of signals that are passed-through. The signals of the argument patch to sndP will appear as the second element of the pair in the resulting patch.

Lift a function to a patch, applying the function to the data input.

Lift a function to a patch, applying the function to the control input.

Given two patches, tuple their data/control inputs and outputs.

Given a homogeneous list (Matrix) of patches, combine them into a single patch, collecting the datacontrol inputsoutputs into matrices.

loopP is a fixpoint style combinator, for backedges.

An instance of the Unit type contains a value that carries no information.

rawReadP reads a binary file into Patch, which will become the lefthand side of a chain of patches.

readPatch reads an encoded file into Patch, which will become the lefthand side of a chain of patches.

rawWriteP runs a complete circuit for the given number of cycles, writing the result to a given file in binary format.

writeP runs a complete circuit for the given number of cycles, writing the result to a given file in string format.

($$) composes two patches serially, sharing a common control protocol. The data output of the first patch is fed to the data input of the second patch. The control output of the second patch is fed to the control input of the first patch, and the control output of the first patch is fed to the control input of the second patch.

readyToAckBridge converts from a ready interface to an ACK interface by preemptively giving the ready signal, and holding the resulting data from the device on the input side if no ACK is received by the device on the output side. If data is currently being held, then the ready signal will not be given. This bridge is fine for deep embedding (can be represented in hardware).

ackToReadyBridge converts from a Ack interface to an Ready interface by ANDing the ready signal from the receiving component with the input enable from the sending component. This may not be necessary at times if the sending component ignores ACKs when no data is sent. This bridge is fine for deep embedding (can be represented in hardware).

This duplicates the incomming datum. This has the behavior that neither branch sees the value until both can recieve it.

This duplicate the incoming datam over many handshaken streams.

unzipP creates a patch that takes in an Enabled data pair, and produces a pair of Enabled data outputs.

matrixUnzipP is the generalization of unzipP to homogeneous matrices.

TODO: Andy write docs for this.

matrixDeMuxP is the generalization of deMuxP to a matrix of signals.

Combine two enabled data inputs into a single Enabled tupled data input.

Extension of zipP to homogeneous matrices.

muxP chooses a the 2nd or 3rd value, based on the Boolean value.

matrixMuxP chooses the n-th value, based on the index value.

FIFO with depth 1.

FIFO with depth 2.

matrixToElementsP turns a matrix into a sequences of elements from the array, in ascending order.

matrixFromElementsP turns a sequence of elements (in ascending order) into a matrix. ascending order.

globalClockP forces the handshaking to use the CLK clock. Which is useful for testing.

cycleP cycles through a constant list (actually a matrix) of values. Generates an async ROM on hardware.

A fabric patch that passes through data and control.

Given two fabric patches, tuple their data/control inputs and outputs.