kansas-lava-0.2.4.5: Kansas Lava is a hardware simulator and VHDL generator.

Safe HaskellNone
LanguageHaskell2010

Language.KansasLava.Utils

Description

This module contains a number of primitive circuits, and instance definitions for standard type classes for circuits.

Synopsis

Documentation

high :: sig ~ Signal i => sig Bool Source #

The Signal representing True.

low :: sig ~ Signal i => sig Bool Source #

The Signal representing False.

and2 :: sig ~ Signal i => sig Bool -> sig Bool -> sig Bool Source #

1-bit and gate.

or2 :: sig ~ Signal i => sig Bool -> sig Bool -> sig Bool Source #

1-bit or gate.

xor2 :: sig ~ Signal i => sig Bool -> sig Bool -> sig Bool Source #

1-bit xor gate.

nand2 :: sig ~ Signal i => sig Bool -> sig Bool -> sig Bool Source #

1-bit nand gate.

nor2 :: sig ~ Signal i => sig Bool -> sig Bool -> sig Bool Source #

1-bit nor gate.

bitNot :: sig ~ Signal i => sig Bool -> sig Bool Source #

1 bit inverter.

testABit :: forall a i w sig. (Bits a, Rep a, Size w, Rep w, w ~ W a, sig ~ Signal i) => sig a -> sig w -> sig Bool Source #

Extract the n'th bit of a signal that can be represented as Bits.

isPositive :: forall sig i ix. (sig ~ Signal i, Size ix, Integral ix, Rep ix) => sig (Signed ix) -> sig Bool Source #

Predicate to see if a Signed value is positive.

(.&&.) :: sig ~ Signal i => sig Bool -> sig Bool -> sig Bool infixr 3 Source #

Alias for and2.

(.||.) :: sig ~ Signal i => sig Bool -> sig Bool -> sig Bool infixr 2 Source #

Alias for or2.

(.^.) :: sig ~ Signal i => sig Bool -> sig Bool -> sig Bool infixr 2 Source #

Alias for xor2.

funMap :: forall sig a b i. (sig ~ Signal i, Rep a, Rep b) => (a -> Maybe b) -> sig a -> sig b Source #

Given a function over a finite domain, generate a ROM representing the function. To make this feasible to implement, we assume that the domain is small (< 2^8 values).

mux :: forall sig a i. (sig ~ Signal i, Rep a) => sig Bool -> (sig a, sig a) -> sig a Source #

Multiplexer with a 1-bit selector and arbitrary width data inputs. zero (false) selects the first argument of the tuple, one (true) selects the second.

muxShallow :: forall a. Rep a => X Bool -> X a -> X a -> X a Source #

Shallow definition of a multiplexer. Deals with 3-value logic.

eval :: forall a. Rep a => a -> () Source #

TODO: Document this. And move it.

evalX :: forall a. Rep a => X a -> () Source #

TODO: Document this.

muxMatrix :: forall sig x a i. (sig ~ Signal i, Size x, Rep x, Rep a) => sig (Matrix x a) -> sig x -> sig a Source #

Alias for .!.

(.!.) :: forall sig x a i. (sig ~ Signal i, Size x, Rep x, Rep a) => sig (Matrix x a) -> sig x -> sig a Source #

Extract the n'th element of a vector.

boolOp :: forall a i sig. (Rep a, sig ~ Signal i) => (a -> a -> Bool) -> String -> sig a -> sig a -> sig Bool Source #

Lift a (named) binary function over bools to be over Signals.

(.==.) :: forall a i sig. (Rep a, Eq a, sig ~ Signal i) => sig a -> sig a -> sig Bool infix 4 Source #

N-bit equality.

(./=.) :: forall a i sig. (Rep a, Eq a, sig ~ Signal i) => sig a -> sig a -> sig Bool Source #

N-bit not-equals.

(.>=.) :: forall a i sig. (Rep a, Ord a, sig ~ Signal i) => sig a -> sig a -> sig Bool infix 4 Source #

N-bit greater-than-or-equals.

(.<=.) :: forall a i sig. (Rep a, Ord a, sig ~ Signal i) => sig a -> sig a -> sig Bool infix 4 Source #

N-bit less-than-or-equals.

(.<.) :: forall a i sig. (Rep a, Ord a, sig ~ Signal i) => sig a -> sig a -> sig Bool infix 4 Source #

N-bit less-than.

(.>.) :: forall a i sig. (Rep a, Ord a, sig ~ Signal i) => sig a -> sig a -> sig Bool infix 4 Source #

N-bit greater-than.

lavaId :: (sig ~ Signal i, Rep a) => sig a -> sig a Source #

The identity function, lifted to Signals.

ignoring :: (sig ~ Signal i, Rep a, Rep b) => sig a -> sig b -> sig a Source #

ignoring is used to make sure a value is reified. TODO: is this used?

cASE :: (Rep b, sig ~ Signal i) => [(sig Bool, sig b)] -> sig b -> sig b Source #

Given a representable value for a discirminant and a list of input signals, generate a n-ary mux.

bitwise :: forall sig a b i. (sig ~ Signal i, Rep a, Rep b, W a ~ W b) => sig a -> sig b Source #

translate using raw underlying bits, Width *must* be the same.

coerce :: forall sig a b i. (sig ~ Signal i, Rep a, Rep b, W a ~ W b) => (a -> b) -> sig a -> sig b Source #

translate using raw underlying bits for deep, but given function for shallow, Width *must* be the same.

signedX :: forall a b. (Rep a, Rep b) => X a -> X b Source #

Coerce a value from on type to another, interpreting the bits as a signed value. Do not sign extend.

signed :: (Rep a, Rep b, Num b, sig ~ Signal i) => sig a -> sig b Source #

consider the bits as signed number (sign extend)

unsignedX :: forall a b. (Rep a, Rep b) => X a -> X b Source #

Consider the value as an unsigned value.

unsigned :: (Rep a, Rep b, Num b, sig ~ Signal i) => sig a -> sig b Source #

consider the bits an unsigned number (zero extend)

mustAssignSLV :: (Rep a, sig ~ Signal i) => sig a -> sig a Source #

force the representation of the incoming argument to be a StdLogicVector. Assumes the argument is an entity; a real hack. We need a type checking pass, instead.

unsafeId :: forall sig a b i. (sig ~ Signal i, Rep a, Rep b) => sig a -> sig b Source #

translate using raw underlying bits, type *must* be the same, but is not statically checked.

unappendS :: forall a a1 a2 sig clk. (sig ~ Signal clk, Rep a, Rep a1, Rep a2, W a ~ ADD (W a1) (W a2)) => sig a -> (sig a1, sig a2) Source #

given a signal of a1 + a2 width, yield a signal with a pair of values of width a1 and a2 respectively.

appendS :: forall sig a b c clk. (sig ~ Signal clk, Rep a, Rep b, Rep c, W c ~ ADD (W a) (W b)) => sig a -> sig b -> sig c Source #

given two signals of a1 and a2 width, respectively, pack them into a signal of a1 + a2 width.

refinesFrom :: forall sig a i. (Clock i, sig ~ Signal i, Rep a) => sig a -> sig a -> sig Bool Source #

The first argument is the value is our value under test; the second is our reference value. If the reference is undefined, then the VUT *can* also be under test. This only works for shallow circuits, and is used when creating test benches.

iterateS :: (Rep a, Clock c, seq ~ Signal c) => (forall j. Signal j a -> Signal j a) -> a -> seq a Source #

Create a register, pass the output of the register through some combinational logic, then pass the result back into the register input.

loopingIncS :: (Bounded a, Eq a, Num a, Rep a, sig ~ Signal i) => sig a -> sig a Source #

loopingDecS :: (Bounded a, Eq a, Num a, Rep a, sig ~ Signal i) => sig a -> sig a Source #