{-# LANGUAGE BangPatterns, CPP, ScopedTypeVariables #-}

-----------------------------------------------------------------------------
--
-- The register allocator
--
-- (c) The University of Glasgow 2004
--
-----------------------------------------------------------------------------

{-
The algorithm is roughly:

  1) Compute strongly connected components of the basic block list.

  2) Compute liveness (mapping from pseudo register to
     point(s) of death?).

  3) Walk instructions in each basic block.  We keep track of
        (a) Free real registers (a bitmap?)
        (b) Current assignment of temporaries to machine registers and/or
            spill slots (call this the "assignment").
        (c) Partial mapping from basic block ids to a virt-to-loc mapping.
            When we first encounter a branch to a basic block,
            we fill in its entry in this table with the current mapping.

     For each instruction:
        (a) For each temporary *read* by the instruction:
            If the temporary does not have a real register allocation:
                - Allocate a real register from the free list.  If
                  the list is empty:
                  - Find a temporary to spill.  Pick one that is
                    not used in this instruction (ToDo: not
                    used for a while...)
                  - generate a spill instruction
                - If the temporary was previously spilled,
                  generate an instruction to read the temp from its spill loc.
            (optimisation: if we can see that a real register is going to
            be used soon, then don't use it for allocation).

        (b) For each real register clobbered by this instruction:
            If a temporary resides in it,
                If the temporary is live after this instruction,
                    Move the temporary to another (non-clobbered & free) reg,
                    or spill it to memory.  Mark the temporary as residing
                    in both memory and a register if it was spilled (it might
                    need to be read by this instruction).

            (ToDo: this is wrong for jump instructions?)

            We do this after step (a), because if we start with
               movq v1, %rsi
            which is an instruction that clobbers %rsi, if v1 currently resides
            in %rsi we want to get
               movq %rsi, %freereg
               movq %rsi, %rsi     -- will disappear
            instead of
               movq %rsi, %freereg
               movq %freereg, %rsi

        (c) Update the current assignment

        (d) If the instruction is a branch:
              if the destination block already has a register assignment,
                Generate a new block with fixup code and redirect the
                jump to the new block.
              else,
                Update the block id->assignment mapping with the current
                assignment.

        (e) Delete all register assignments for temps which are read
            (only) and die here.  Update the free register list.

        (f) Mark all registers clobbered by this instruction as not free,
            and mark temporaries which have been spilled due to clobbering
            as in memory (step (a) marks then as in both mem & reg).

        (g) For each temporary *written* by this instruction:
            Allocate a real register as for (b), spilling something
            else if necessary.
                - except when updating the assignment, drop any memory
                  locations that the temporary was previously in, since
                  they will be no longer valid after this instruction.

        (h) Delete all register assignments for temps which are
            written and die here (there should rarely be any).  Update
            the free register list.

        (i) Rewrite the instruction with the new mapping.

        (j) For each spilled reg known to be now dead, re-add its stack slot
            to the free list.

-}

module RegAlloc.Linear.Main (
        regAlloc,
        module  RegAlloc.Linear.Base,
        module  RegAlloc.Linear.Stats
  ) where

#include "HsVersions.h"


import GhcPrelude

import RegAlloc.Linear.State
import RegAlloc.Linear.Base
import RegAlloc.Linear.StackMap
import RegAlloc.Linear.FreeRegs
import RegAlloc.Linear.Stats
import RegAlloc.Linear.JoinToTargets
import qualified RegAlloc.Linear.PPC.FreeRegs    as PPC
import qualified RegAlloc.Linear.SPARC.FreeRegs  as SPARC
import qualified RegAlloc.Linear.X86.FreeRegs    as X86
import qualified RegAlloc.Linear.X86_64.FreeRegs as X86_64
import TargetReg
import RegAlloc.Liveness
import Instruction
import Reg

import BlockId
import Hoopl.Collections
import Cmm hiding (RegSet)

import Digraph
import DynFlags
import Unique
import UniqSet
import UniqFM
import UniqSupply
import Outputable
import GHC.Platform

import Data.Maybe
import Data.List
import Control.Monad

-- -----------------------------------------------------------------------------
-- Top level of the register allocator

-- Allocate registers
regAlloc
        :: (Outputable instr, Instruction instr)
        => DynFlags
        -> LiveCmmDecl statics instr
        -> UniqSM ( NatCmmDecl statics instr
                  , Maybe Int  -- number of extra stack slots required,
                               -- beyond maxSpillSlots
                  , Maybe RegAllocStats
                  )

regAlloc :: DynFlags
-> LiveCmmDecl statics instr
-> UniqSM
     (NatCmmDecl statics instr, Maybe Int, Maybe RegAllocStats)
regAlloc DynFlags
_ (CmmData Section
sec statics
d)
        = (NatCmmDecl statics instr, Maybe Int, Maybe RegAllocStats)
-> UniqSM
     (NatCmmDecl statics instr, Maybe Int, Maybe RegAllocStats)
forall (m :: * -> *) a. Monad m => a -> m a
return
                ( Section -> statics -> NatCmmDecl statics instr
forall d h g. Section -> d -> GenCmmDecl d h g
CmmData Section
sec statics
d
                , Maybe Int
forall a. Maybe a
Nothing
                , Maybe RegAllocStats
forall a. Maybe a
Nothing )

regAlloc DynFlags
_ (CmmProc (LiveInfo LabelMap CmmStatics
info [BlockId]
_ BlockMap RegSet
_ BlockMap IntSet
_) CLabel
lbl [GlobalReg]
live [])
        = (NatCmmDecl statics instr, Maybe Int, Maybe RegAllocStats)
-> UniqSM
     (NatCmmDecl statics instr, Maybe Int, Maybe RegAllocStats)
forall (m :: * -> *) a. Monad m => a -> m a
return ( LabelMap CmmStatics
-> CLabel
-> [GlobalReg]
-> ListGraph instr
-> NatCmmDecl statics instr
forall d h g. h -> CLabel -> [GlobalReg] -> g -> GenCmmDecl d h g
CmmProc LabelMap CmmStatics
info CLabel
lbl [GlobalReg]
live ([GenBasicBlock instr] -> ListGraph instr
forall i. [GenBasicBlock i] -> ListGraph i
ListGraph [])
                 , Maybe Int
forall a. Maybe a
Nothing
                 , Maybe RegAllocStats
forall a. Maybe a
Nothing )

regAlloc DynFlags
dflags (CmmProc LiveInfo
static CLabel
lbl [GlobalReg]
live [SCC (LiveBasicBlock instr)]
sccs)
        | LiveInfo LabelMap CmmStatics
info entry_ids :: [BlockId]
entry_ids@(BlockId
first_id:[BlockId]
_) BlockMap RegSet
block_live BlockMap IntSet
_ <- LiveInfo
static
        = do
                -- do register allocation on each component.
                ([GenBasicBlock instr]
final_blocks, RegAllocStats
stats, Int
stack_use)
                        <- DynFlags
-> [BlockId]
-> BlockMap RegSet
-> [SCC (LiveBasicBlock instr)]
-> UniqSM ([GenBasicBlock instr], RegAllocStats, Int)
forall instr.
(Outputable instr, Instruction instr) =>
DynFlags
-> [BlockId]
-> BlockMap RegSet
-> [SCC (LiveBasicBlock instr)]
-> UniqSM ([NatBasicBlock instr], RegAllocStats, Int)
linearRegAlloc DynFlags
dflags [BlockId]
entry_ids BlockMap RegSet
block_live [SCC (LiveBasicBlock instr)]
sccs

                -- make sure the block that was first in the input list
                --      stays at the front of the output
                let ((GenBasicBlock instr
first':[GenBasicBlock instr]
_), [GenBasicBlock instr]
rest')
                                = (GenBasicBlock instr -> Bool)
-> [GenBasicBlock instr]
-> ([GenBasicBlock instr], [GenBasicBlock instr])
forall a. (a -> Bool) -> [a] -> ([a], [a])
partition ((BlockId -> BlockId -> Bool
forall a. Eq a => a -> a -> Bool
== BlockId
first_id) (BlockId -> Bool)
-> (GenBasicBlock instr -> BlockId) -> GenBasicBlock instr -> Bool
forall b c a. (b -> c) -> (a -> b) -> a -> c
. GenBasicBlock instr -> BlockId
forall i. GenBasicBlock i -> BlockId
blockId) [GenBasicBlock instr]
final_blocks

                let max_spill_slots :: Int
max_spill_slots = DynFlags -> Int
maxSpillSlots DynFlags
dflags
                    extra_stack :: Maybe Int
extra_stack
                      | Int
stack_use Int -> Int -> Bool
forall a. Ord a => a -> a -> Bool
> Int
max_spill_slots
                      = Int -> Maybe Int
forall a. a -> Maybe a
Just (Int
stack_use Int -> Int -> Int
forall a. Num a => a -> a -> a
- Int
max_spill_slots)
                      | Bool
otherwise
                      = Maybe Int
forall a. Maybe a
Nothing

                (NatCmmDecl statics instr, Maybe Int, Maybe RegAllocStats)
-> UniqSM
     (NatCmmDecl statics instr, Maybe Int, Maybe RegAllocStats)
forall (m :: * -> *) a. Monad m => a -> m a
return  ( LabelMap CmmStatics
-> CLabel
-> [GlobalReg]
-> ListGraph instr
-> NatCmmDecl statics instr
forall d h g. h -> CLabel -> [GlobalReg] -> g -> GenCmmDecl d h g
CmmProc LabelMap CmmStatics
info CLabel
lbl [GlobalReg]
live ([GenBasicBlock instr] -> ListGraph instr
forall i. [GenBasicBlock i] -> ListGraph i
ListGraph (GenBasicBlock instr
first' GenBasicBlock instr
-> [GenBasicBlock instr] -> [GenBasicBlock instr]
forall a. a -> [a] -> [a]
: [GenBasicBlock instr]
rest'))
                        , Maybe Int
extra_stack
                        , RegAllocStats -> Maybe RegAllocStats
forall a. a -> Maybe a
Just RegAllocStats
stats)

-- bogus. to make non-exhaustive match warning go away.
regAlloc DynFlags
_ (CmmProc LiveInfo
_ CLabel
_ [GlobalReg]
_ [SCC (LiveBasicBlock instr)]
_)
        = String
-> UniqSM
     (NatCmmDecl statics instr, Maybe Int, Maybe RegAllocStats)
forall a. String -> a
panic String
"RegAllocLinear.regAlloc: no match"


-- -----------------------------------------------------------------------------
-- Linear sweep to allocate registers


-- | Do register allocation on some basic blocks.
--   But be careful to allocate a block in an SCC only if it has
--   an entry in the block map or it is the first block.
--
linearRegAlloc
        :: (Outputable instr, Instruction instr)
        => DynFlags
        -> [BlockId] -- ^ entry points
        -> BlockMap RegSet
              -- ^ live regs on entry to each basic block
        -> [SCC (LiveBasicBlock instr)]
              -- ^ instructions annotated with "deaths"
        -> UniqSM ([NatBasicBlock instr], RegAllocStats, Int)

linearRegAlloc :: DynFlags
-> [BlockId]
-> BlockMap RegSet
-> [SCC (LiveBasicBlock instr)]
-> UniqSM ([NatBasicBlock instr], RegAllocStats, Int)
linearRegAlloc DynFlags
dflags [BlockId]
entry_ids BlockMap RegSet
block_live [SCC (LiveBasicBlock instr)]
sccs
 = case Platform -> Arch
platformArch Platform
platform of
      Arch
ArchX86        -> FreeRegs -> UniqSM ([NatBasicBlock instr], RegAllocStats, Int)
forall freeRegs.
FR freeRegs =>
freeRegs -> UniqSM ([NatBasicBlock instr], RegAllocStats, Int)
go (FreeRegs -> UniqSM ([NatBasicBlock instr], RegAllocStats, Int))
-> FreeRegs -> UniqSM ([NatBasicBlock instr], RegAllocStats, Int)
forall a b. (a -> b) -> a -> b
$ (Platform -> FreeRegs
forall freeRegs. FR freeRegs => Platform -> freeRegs
frInitFreeRegs Platform
platform :: X86.FreeRegs)
      Arch
ArchX86_64     -> FreeRegs -> UniqSM ([NatBasicBlock instr], RegAllocStats, Int)
forall freeRegs.
FR freeRegs =>
freeRegs -> UniqSM ([NatBasicBlock instr], RegAllocStats, Int)
go (FreeRegs -> UniqSM ([NatBasicBlock instr], RegAllocStats, Int))
-> FreeRegs -> UniqSM ([NatBasicBlock instr], RegAllocStats, Int)
forall a b. (a -> b) -> a -> b
$ (Platform -> FreeRegs
forall freeRegs. FR freeRegs => Platform -> freeRegs
frInitFreeRegs Platform
platform :: X86_64.FreeRegs)
      Arch
ArchS390X      -> String -> UniqSM ([NatBasicBlock instr], RegAllocStats, Int)
forall a. String -> a
panic String
"linearRegAlloc ArchS390X"
      Arch
ArchSPARC      -> FreeRegs -> UniqSM ([NatBasicBlock instr], RegAllocStats, Int)
forall freeRegs.
FR freeRegs =>
freeRegs -> UniqSM ([NatBasicBlock instr], RegAllocStats, Int)
go (FreeRegs -> UniqSM ([NatBasicBlock instr], RegAllocStats, Int))
-> FreeRegs -> UniqSM ([NatBasicBlock instr], RegAllocStats, Int)
forall a b. (a -> b) -> a -> b
$ (Platform -> FreeRegs
forall freeRegs. FR freeRegs => Platform -> freeRegs
frInitFreeRegs Platform
platform :: SPARC.FreeRegs)
      Arch
ArchSPARC64    -> String -> UniqSM ([NatBasicBlock instr], RegAllocStats, Int)
forall a. String -> a
panic String
"linearRegAlloc ArchSPARC64"
      Arch
ArchPPC        -> FreeRegs -> UniqSM ([NatBasicBlock instr], RegAllocStats, Int)
forall freeRegs.
FR freeRegs =>
freeRegs -> UniqSM ([NatBasicBlock instr], RegAllocStats, Int)
go (FreeRegs -> UniqSM ([NatBasicBlock instr], RegAllocStats, Int))
-> FreeRegs -> UniqSM ([NatBasicBlock instr], RegAllocStats, Int)
forall a b. (a -> b) -> a -> b
$ (Platform -> FreeRegs
forall freeRegs. FR freeRegs => Platform -> freeRegs
frInitFreeRegs Platform
platform :: PPC.FreeRegs)
      ArchARM ArmISA
_ [ArmISAExt]
_ ArmABI
_  -> String -> UniqSM ([NatBasicBlock instr], RegAllocStats, Int)
forall a. String -> a
panic String
"linearRegAlloc ArchARM"
      Arch
ArchARM64      -> String -> UniqSM ([NatBasicBlock instr], RegAllocStats, Int)
forall a. String -> a
panic String
"linearRegAlloc ArchARM64"
      ArchPPC_64 PPC_64ABI
_   -> FreeRegs -> UniqSM ([NatBasicBlock instr], RegAllocStats, Int)
forall freeRegs.
FR freeRegs =>
freeRegs -> UniqSM ([NatBasicBlock instr], RegAllocStats, Int)
go (FreeRegs -> UniqSM ([NatBasicBlock instr], RegAllocStats, Int))
-> FreeRegs -> UniqSM ([NatBasicBlock instr], RegAllocStats, Int)
forall a b. (a -> b) -> a -> b
$ (Platform -> FreeRegs
forall freeRegs. FR freeRegs => Platform -> freeRegs
frInitFreeRegs Platform
platform :: PPC.FreeRegs)
      Arch
ArchAlpha      -> String -> UniqSM ([NatBasicBlock instr], RegAllocStats, Int)
forall a. String -> a
panic String
"linearRegAlloc ArchAlpha"
      Arch
ArchMipseb     -> String -> UniqSM ([NatBasicBlock instr], RegAllocStats, Int)
forall a. String -> a
panic String
"linearRegAlloc ArchMipseb"
      Arch
ArchMipsel     -> String -> UniqSM ([NatBasicBlock instr], RegAllocStats, Int)
forall a. String -> a
panic String
"linearRegAlloc ArchMipsel"
      Arch
ArchJavaScript -> String -> UniqSM ([NatBasicBlock instr], RegAllocStats, Int)
forall a. String -> a
panic String
"linearRegAlloc ArchJavaScript"
      Arch
ArchUnknown    -> String -> UniqSM ([NatBasicBlock instr], RegAllocStats, Int)
forall a. String -> a
panic String
"linearRegAlloc ArchUnknown"
 where
  go :: freeRegs -> UniqSM ([NatBasicBlock instr], RegAllocStats, Int)
go freeRegs
f = DynFlags
-> freeRegs
-> [BlockId]
-> BlockMap RegSet
-> [SCC (LiveBasicBlock instr)]
-> UniqSM ([NatBasicBlock instr], RegAllocStats, Int)
forall freeRegs instr.
(FR freeRegs, Outputable instr, Instruction instr) =>
DynFlags
-> freeRegs
-> [BlockId]
-> BlockMap RegSet
-> [SCC (LiveBasicBlock instr)]
-> UniqSM ([NatBasicBlock instr], RegAllocStats, Int)
linearRegAlloc' DynFlags
dflags freeRegs
f [BlockId]
entry_ids BlockMap RegSet
block_live [SCC (LiveBasicBlock instr)]
sccs
  platform :: Platform
platform = DynFlags -> Platform
targetPlatform DynFlags
dflags

linearRegAlloc'
        :: (FR freeRegs, Outputable instr, Instruction instr)
        => DynFlags
        -> freeRegs
        -> [BlockId]                    -- ^ entry points
        -> BlockMap RegSet              -- ^ live regs on entry to each basic block
        -> [SCC (LiveBasicBlock instr)] -- ^ instructions annotated with "deaths"
        -> UniqSM ([NatBasicBlock instr], RegAllocStats, Int)

linearRegAlloc' :: DynFlags
-> freeRegs
-> [BlockId]
-> BlockMap RegSet
-> [SCC (LiveBasicBlock instr)]
-> UniqSM ([NatBasicBlock instr], RegAllocStats, Int)
linearRegAlloc' DynFlags
dflags freeRegs
initFreeRegs [BlockId]
entry_ids BlockMap RegSet
block_live [SCC (LiveBasicBlock instr)]
sccs
 = do   UniqSupply
us      <- UniqSM UniqSupply
forall (m :: * -> *). MonadUnique m => m UniqSupply
getUniqueSupplyM
        let (BlockAssignment freeRegs
_, StackMap
stack, RegAllocStats
stats, [NatBasicBlock instr]
blocks) =
                DynFlags
-> BlockAssignment freeRegs
-> freeRegs
-> RegMap Loc
-> StackMap
-> UniqSupply
-> RegM freeRegs [NatBasicBlock instr]
-> (BlockAssignment freeRegs, StackMap, RegAllocStats,
    [NatBasicBlock instr])
forall freeRegs a.
DynFlags
-> BlockAssignment freeRegs
-> freeRegs
-> RegMap Loc
-> StackMap
-> UniqSupply
-> RegM freeRegs a
-> (BlockAssignment freeRegs, StackMap, RegAllocStats, a)
runR DynFlags
dflags BlockAssignment freeRegs
forall (map :: * -> *) a. IsMap map => map a
mapEmpty freeRegs
initFreeRegs RegMap Loc
forall a. UniqFM a
emptyRegMap (DynFlags -> StackMap
emptyStackMap DynFlags
dflags) UniqSupply
us
                    (RegM freeRegs [NatBasicBlock instr]
 -> (BlockAssignment freeRegs, StackMap, RegAllocStats,
     [NatBasicBlock instr]))
-> RegM freeRegs [NatBasicBlock instr]
-> (BlockAssignment freeRegs, StackMap, RegAllocStats,
    [NatBasicBlock instr])
forall a b. (a -> b) -> a -> b
$ [BlockId]
-> BlockMap RegSet
-> [NatBasicBlock instr]
-> [SCC (LiveBasicBlock instr)]
-> RegM freeRegs [NatBasicBlock instr]
forall freeRegs instr.
(FR freeRegs, Instruction instr, Outputable instr) =>
[BlockId]
-> BlockMap RegSet
-> [NatBasicBlock instr]
-> [SCC (LiveBasicBlock instr)]
-> RegM freeRegs [NatBasicBlock instr]
linearRA_SCCs [BlockId]
entry_ids BlockMap RegSet
block_live [] [SCC (LiveBasicBlock instr)]
sccs
        ([NatBasicBlock instr], RegAllocStats, Int)
-> UniqSM ([NatBasicBlock instr], RegAllocStats, Int)
forall (m :: * -> *) a. Monad m => a -> m a
return  ([NatBasicBlock instr]
blocks, RegAllocStats
stats, StackMap -> Int
getStackUse StackMap
stack)


linearRA_SCCs :: (FR freeRegs, Instruction instr, Outputable instr)
              => [BlockId]
              -> BlockMap RegSet
              -> [NatBasicBlock instr]
              -> [SCC (LiveBasicBlock instr)]
              -> RegM freeRegs [NatBasicBlock instr]

linearRA_SCCs :: [BlockId]
-> BlockMap RegSet
-> [NatBasicBlock instr]
-> [SCC (LiveBasicBlock instr)]
-> RegM freeRegs [NatBasicBlock instr]
linearRA_SCCs [BlockId]
_ BlockMap RegSet
_ [NatBasicBlock instr]
blocksAcc []
        = [NatBasicBlock instr] -> RegM freeRegs [NatBasicBlock instr]
forall (m :: * -> *) a. Monad m => a -> m a
return ([NatBasicBlock instr] -> RegM freeRegs [NatBasicBlock instr])
-> [NatBasicBlock instr] -> RegM freeRegs [NatBasicBlock instr]
forall a b. (a -> b) -> a -> b
$ [NatBasicBlock instr] -> [NatBasicBlock instr]
forall a. [a] -> [a]
reverse [NatBasicBlock instr]
blocksAcc

linearRA_SCCs [BlockId]
entry_ids BlockMap RegSet
block_live [NatBasicBlock instr]
blocksAcc (AcyclicSCC LiveBasicBlock instr
block : [SCC (LiveBasicBlock instr)]
sccs)
 = do   [NatBasicBlock instr]
blocks' <- BlockMap RegSet
-> LiveBasicBlock instr -> RegM freeRegs [NatBasicBlock instr]
forall freeRegs instr.
(FR freeRegs, Outputable instr, Instruction instr) =>
BlockMap RegSet
-> LiveBasicBlock instr -> RegM freeRegs [NatBasicBlock instr]
processBlock BlockMap RegSet
block_live LiveBasicBlock instr
block
        [BlockId]
-> BlockMap RegSet
-> [NatBasicBlock instr]
-> [SCC (LiveBasicBlock instr)]
-> RegM freeRegs [NatBasicBlock instr]
forall freeRegs instr.
(FR freeRegs, Instruction instr, Outputable instr) =>
[BlockId]
-> BlockMap RegSet
-> [NatBasicBlock instr]
-> [SCC (LiveBasicBlock instr)]
-> RegM freeRegs [NatBasicBlock instr]
linearRA_SCCs [BlockId]
entry_ids BlockMap RegSet
block_live
                (([NatBasicBlock instr] -> [NatBasicBlock instr]
forall a. [a] -> [a]
reverse [NatBasicBlock instr]
blocks') [NatBasicBlock instr]
-> [NatBasicBlock instr] -> [NatBasicBlock instr]
forall a. [a] -> [a] -> [a]
++ [NatBasicBlock instr]
blocksAcc)
                [SCC (LiveBasicBlock instr)]
sccs

linearRA_SCCs [BlockId]
entry_ids BlockMap RegSet
block_live [NatBasicBlock instr]
blocksAcc (CyclicSCC [LiveBasicBlock instr]
blocks : [SCC (LiveBasicBlock instr)]
sccs)
 = do
        [[NatBasicBlock instr]]
blockss' <- [BlockId]
-> BlockMap RegSet
-> [LiveBasicBlock instr]
-> [LiveBasicBlock instr]
-> [[NatBasicBlock instr]]
-> Bool
-> RegM freeRegs [[NatBasicBlock instr]]
forall freeRegs instr.
(FR freeRegs, Instruction instr, Outputable instr) =>
[BlockId]
-> BlockMap RegSet
-> [GenBasicBlock (LiveInstr instr)]
-> [GenBasicBlock (LiveInstr instr)]
-> [[NatBasicBlock instr]]
-> Bool
-> RegM freeRegs [[NatBasicBlock instr]]
process [BlockId]
entry_ids BlockMap RegSet
block_live [LiveBasicBlock instr]
blocks [] ([NatBasicBlock instr] -> [[NatBasicBlock instr]]
forall (m :: * -> *) a. Monad m => a -> m a
return []) Bool
False
        [BlockId]
-> BlockMap RegSet
-> [NatBasicBlock instr]
-> [SCC (LiveBasicBlock instr)]
-> RegM freeRegs [NatBasicBlock instr]
forall freeRegs instr.
(FR freeRegs, Instruction instr, Outputable instr) =>
[BlockId]
-> BlockMap RegSet
-> [NatBasicBlock instr]
-> [SCC (LiveBasicBlock instr)]
-> RegM freeRegs [NatBasicBlock instr]
linearRA_SCCs [BlockId]
entry_ids BlockMap RegSet
block_live
                ([NatBasicBlock instr] -> [NatBasicBlock instr]
forall a. [a] -> [a]
reverse ([[NatBasicBlock instr]] -> [NatBasicBlock instr]
forall (t :: * -> *) a. Foldable t => t [a] -> [a]
concat [[NatBasicBlock instr]]
blockss') [NatBasicBlock instr]
-> [NatBasicBlock instr] -> [NatBasicBlock instr]
forall a. [a] -> [a] -> [a]
++ [NatBasicBlock instr]
blocksAcc)
                [SCC (LiveBasicBlock instr)]
sccs

{- from John Dias's patch 2008/10/16:
   The linear-scan allocator sometimes allocates a block
   before allocating one of its predecessors, which could lead to
   inconsistent allocations. Make it so a block is only allocated
   if a predecessor has set the "incoming" assignments for the block, or
   if it's the procedure's entry block.

   BL 2009/02: Careful. If the assignment for a block doesn't get set for
   some reason then this function will loop. We should probably do some
   more sanity checking to guard against this eventuality.
-}

process :: (FR freeRegs, Instruction instr, Outputable instr)
        => [BlockId]
        -> BlockMap RegSet
        -> [GenBasicBlock (LiveInstr instr)]
        -> [GenBasicBlock (LiveInstr instr)]
        -> [[NatBasicBlock instr]]
        -> Bool
        -> RegM freeRegs [[NatBasicBlock instr]]

process :: [BlockId]
-> BlockMap RegSet
-> [GenBasicBlock (LiveInstr instr)]
-> [GenBasicBlock (LiveInstr instr)]
-> [[NatBasicBlock instr]]
-> Bool
-> RegM freeRegs [[NatBasicBlock instr]]
process [BlockId]
_ BlockMap RegSet
_ [] []         [[NatBasicBlock instr]]
accum Bool
_
        = [[NatBasicBlock instr]] -> RegM freeRegs [[NatBasicBlock instr]]
forall (m :: * -> *) a. Monad m => a -> m a
return ([[NatBasicBlock instr]] -> RegM freeRegs [[NatBasicBlock instr]])
-> [[NatBasicBlock instr]] -> RegM freeRegs [[NatBasicBlock instr]]
forall a b. (a -> b) -> a -> b
$ [[NatBasicBlock instr]] -> [[NatBasicBlock instr]]
forall a. [a] -> [a]
reverse [[NatBasicBlock instr]]
accum

process [BlockId]
entry_ids BlockMap RegSet
block_live [] [GenBasicBlock (LiveInstr instr)]
next_round [[NatBasicBlock instr]]
accum Bool
madeProgress
        | Bool -> Bool
not Bool
madeProgress

          {- BUGS: There are so many unreachable blocks in the code the warnings are overwhelming.
             pprTrace "RegAlloc.Linear.Main.process: no progress made, bailing out."
                (  text "Unreachable blocks:"
                $$ vcat (map ppr next_round)) -}
        = [[NatBasicBlock instr]] -> RegM freeRegs [[NatBasicBlock instr]]
forall (m :: * -> *) a. Monad m => a -> m a
return ([[NatBasicBlock instr]] -> RegM freeRegs [[NatBasicBlock instr]])
-> [[NatBasicBlock instr]] -> RegM freeRegs [[NatBasicBlock instr]]
forall a b. (a -> b) -> a -> b
$ [[NatBasicBlock instr]] -> [[NatBasicBlock instr]]
forall a. [a] -> [a]
reverse [[NatBasicBlock instr]]
accum

        | Bool
otherwise
        = [BlockId]
-> BlockMap RegSet
-> [GenBasicBlock (LiveInstr instr)]
-> [GenBasicBlock (LiveInstr instr)]
-> [[NatBasicBlock instr]]
-> Bool
-> RegM freeRegs [[NatBasicBlock instr]]
forall freeRegs instr.
(FR freeRegs, Instruction instr, Outputable instr) =>
[BlockId]
-> BlockMap RegSet
-> [GenBasicBlock (LiveInstr instr)]
-> [GenBasicBlock (LiveInstr instr)]
-> [[NatBasicBlock instr]]
-> Bool
-> RegM freeRegs [[NatBasicBlock instr]]
process [BlockId]
entry_ids BlockMap RegSet
block_live
                  [GenBasicBlock (LiveInstr instr)]
next_round [] [[NatBasicBlock instr]]
accum Bool
False

process [BlockId]
entry_ids BlockMap RegSet
block_live (b :: GenBasicBlock (LiveInstr instr)
b@(BasicBlock BlockId
id [LiveInstr instr]
_) : [GenBasicBlock (LiveInstr instr)]
blocks)
        [GenBasicBlock (LiveInstr instr)]
next_round [[NatBasicBlock instr]]
accum Bool
madeProgress
 = do
        BlockAssignment freeRegs
block_assig <- RegM freeRegs (BlockAssignment freeRegs)
forall freeRegs. RegM freeRegs (BlockAssignment freeRegs)
getBlockAssigR

        if Maybe (freeRegs, RegMap Loc) -> Bool
forall a. Maybe a -> Bool
isJust (KeyOf LabelMap
-> BlockAssignment freeRegs -> Maybe (freeRegs, RegMap Loc)
forall (map :: * -> *) a.
IsMap map =>
KeyOf map -> map a -> Maybe a
mapLookup KeyOf LabelMap
BlockId
id BlockAssignment freeRegs
block_assig)
             Bool -> Bool -> Bool
|| BlockId
id BlockId -> [BlockId] -> Bool
forall (t :: * -> *) a. (Foldable t, Eq a) => a -> t a -> Bool
`elem` [BlockId]
entry_ids
         then do
                [NatBasicBlock instr]
b'  <- BlockMap RegSet
-> GenBasicBlock (LiveInstr instr)
-> RegM freeRegs [NatBasicBlock instr]
forall freeRegs instr.
(FR freeRegs, Outputable instr, Instruction instr) =>
BlockMap RegSet
-> LiveBasicBlock instr -> RegM freeRegs [NatBasicBlock instr]
processBlock BlockMap RegSet
block_live GenBasicBlock (LiveInstr instr)
b
                [BlockId]
-> BlockMap RegSet
-> [GenBasicBlock (LiveInstr instr)]
-> [GenBasicBlock (LiveInstr instr)]
-> [[NatBasicBlock instr]]
-> Bool
-> RegM freeRegs [[NatBasicBlock instr]]
forall freeRegs instr.
(FR freeRegs, Instruction instr, Outputable instr) =>
[BlockId]
-> BlockMap RegSet
-> [GenBasicBlock (LiveInstr instr)]
-> [GenBasicBlock (LiveInstr instr)]
-> [[NatBasicBlock instr]]
-> Bool
-> RegM freeRegs [[NatBasicBlock instr]]
process [BlockId]
entry_ids BlockMap RegSet
block_live [GenBasicBlock (LiveInstr instr)]
blocks
                        [GenBasicBlock (LiveInstr instr)]
next_round ([NatBasicBlock instr]
b' [NatBasicBlock instr]
-> [[NatBasicBlock instr]] -> [[NatBasicBlock instr]]
forall a. a -> [a] -> [a]
: [[NatBasicBlock instr]]
accum) Bool
True

         else   [BlockId]
-> BlockMap RegSet
-> [GenBasicBlock (LiveInstr instr)]
-> [GenBasicBlock (LiveInstr instr)]
-> [[NatBasicBlock instr]]
-> Bool
-> RegM freeRegs [[NatBasicBlock instr]]
forall freeRegs instr.
(FR freeRegs, Instruction instr, Outputable instr) =>
[BlockId]
-> BlockMap RegSet
-> [GenBasicBlock (LiveInstr instr)]
-> [GenBasicBlock (LiveInstr instr)]
-> [[NatBasicBlock instr]]
-> Bool
-> RegM freeRegs [[NatBasicBlock instr]]
process [BlockId]
entry_ids BlockMap RegSet
block_live [GenBasicBlock (LiveInstr instr)]
blocks
                        (GenBasicBlock (LiveInstr instr)
b GenBasicBlock (LiveInstr instr)
-> [GenBasicBlock (LiveInstr instr)]
-> [GenBasicBlock (LiveInstr instr)]
forall a. a -> [a] -> [a]
: [GenBasicBlock (LiveInstr instr)]
next_round) [[NatBasicBlock instr]]
accum Bool
madeProgress


-- | Do register allocation on this basic block
--
processBlock
        :: (FR freeRegs, Outputable instr, Instruction instr)
        => BlockMap RegSet              -- ^ live regs on entry to each basic block
        -> LiveBasicBlock instr         -- ^ block to do register allocation on
        -> RegM freeRegs [NatBasicBlock instr]   -- ^ block with registers allocated

processBlock :: BlockMap RegSet
-> LiveBasicBlock instr -> RegM freeRegs [NatBasicBlock instr]
processBlock BlockMap RegSet
block_live (BasicBlock BlockId
id [LiveInstr instr]
instrs)
 = do   BlockId -> BlockMap RegSet -> RegM freeRegs ()
forall freeRegs.
FR freeRegs =>
BlockId -> BlockMap RegSet -> RegM freeRegs ()
initBlock BlockId
id BlockMap RegSet
block_live
        ([instr]
instrs', [NatBasicBlock instr]
fixups)
                <- BlockMap RegSet
-> [instr]
-> [NatBasicBlock instr]
-> BlockId
-> [LiveInstr instr]
-> RegM freeRegs ([instr], [NatBasicBlock instr])
forall freeRegs instr.
(FR freeRegs, Outputable instr, Instruction instr) =>
BlockMap RegSet
-> [instr]
-> [NatBasicBlock instr]
-> BlockId
-> [LiveInstr instr]
-> RegM freeRegs ([instr], [NatBasicBlock instr])
linearRA BlockMap RegSet
block_live [] [] BlockId
id [LiveInstr instr]
instrs
        [NatBasicBlock instr] -> RegM freeRegs [NatBasicBlock instr]
forall (m :: * -> *) a. Monad m => a -> m a
return  ([NatBasicBlock instr] -> RegM freeRegs [NatBasicBlock instr])
-> [NatBasicBlock instr] -> RegM freeRegs [NatBasicBlock instr]
forall a b. (a -> b) -> a -> b
$ BlockId -> [instr] -> NatBasicBlock instr
forall i. BlockId -> [i] -> GenBasicBlock i
BasicBlock BlockId
id [instr]
instrs' NatBasicBlock instr
-> [NatBasicBlock instr] -> [NatBasicBlock instr]
forall a. a -> [a] -> [a]
: [NatBasicBlock instr]
fixups


-- | Load the freeregs and current reg assignment into the RegM state
--      for the basic block with this BlockId.
initBlock :: FR freeRegs
          => BlockId -> BlockMap RegSet -> RegM freeRegs ()
initBlock :: BlockId -> BlockMap RegSet -> RegM freeRegs ()
initBlock BlockId
id BlockMap RegSet
block_live
 = do   DynFlags
dflags <- RegM freeRegs DynFlags
forall (m :: * -> *). HasDynFlags m => m DynFlags
getDynFlags
        let platform :: Platform
platform = DynFlags -> Platform
targetPlatform DynFlags
dflags
        BlockAssignment freeRegs
block_assig     <- RegM freeRegs (BlockAssignment freeRegs)
forall freeRegs. RegM freeRegs (BlockAssignment freeRegs)
getBlockAssigR
        case KeyOf LabelMap
-> BlockAssignment freeRegs -> Maybe (freeRegs, RegMap Loc)
forall (map :: * -> *) a.
IsMap map =>
KeyOf map -> map a -> Maybe a
mapLookup KeyOf LabelMap
BlockId
id BlockAssignment freeRegs
block_assig of
                -- no prior info about this block: we must consider
                -- any fixed regs to be allocated, but we can ignore
                -- virtual regs (presumably this is part of a loop,
                -- and we'll iterate again).  The assignment begins
                -- empty.
                Maybe (freeRegs, RegMap Loc)
Nothing
                 -> do  -- pprTrace "initFreeRegs" (text $ show initFreeRegs) (return ())
                        case KeyOf LabelMap -> BlockMap RegSet -> Maybe RegSet
forall (map :: * -> *) a.
IsMap map =>
KeyOf map -> map a -> Maybe a
mapLookup KeyOf LabelMap
BlockId
id BlockMap RegSet
block_live of
                          Maybe RegSet
Nothing ->
                            freeRegs -> RegM freeRegs ()
forall freeRegs. freeRegs -> RegM freeRegs ()
setFreeRegsR    (Platform -> freeRegs
forall freeRegs. FR freeRegs => Platform -> freeRegs
frInitFreeRegs Platform
platform)
                          Just RegSet
live ->
                            freeRegs -> RegM freeRegs ()
forall freeRegs. freeRegs -> RegM freeRegs ()
setFreeRegsR (freeRegs -> RegM freeRegs ()) -> freeRegs -> RegM freeRegs ()
forall a b. (a -> b) -> a -> b
$ (freeRegs -> RealReg -> freeRegs)
-> freeRegs -> [RealReg] -> freeRegs
forall (t :: * -> *) b a.
Foldable t =>
(b -> a -> b) -> b -> t a -> b
foldl' ((RealReg -> freeRegs -> freeRegs)
-> freeRegs -> RealReg -> freeRegs
forall a b c. (a -> b -> c) -> b -> a -> c
flip ((RealReg -> freeRegs -> freeRegs)
 -> freeRegs -> RealReg -> freeRegs)
-> (RealReg -> freeRegs -> freeRegs)
-> freeRegs
-> RealReg
-> freeRegs
forall a b. (a -> b) -> a -> b
$ Platform -> RealReg -> freeRegs -> freeRegs
forall freeRegs.
FR freeRegs =>
Platform -> RealReg -> freeRegs -> freeRegs
frAllocateReg Platform
platform) (Platform -> freeRegs
forall freeRegs. FR freeRegs => Platform -> freeRegs
frInitFreeRegs Platform
platform)
                                                  [ RealReg
r | RegReal RealReg
r <- RegSet -> [Reg]
forall elt. UniqSet elt -> [elt]
nonDetEltsUniqSet RegSet
live ]
                            -- See Note [Unique Determinism and code generation]
                        RegMap Loc -> RegM freeRegs ()
forall freeRegs. RegMap Loc -> RegM freeRegs ()
setAssigR       RegMap Loc
forall a. UniqFM a
emptyRegMap

                -- load info about register assignments leading into this block.
                Just (freeRegs
freeregs, RegMap Loc
assig)
                 -> do  freeRegs -> RegM freeRegs ()
forall freeRegs. freeRegs -> RegM freeRegs ()
setFreeRegsR    freeRegs
freeregs
                        RegMap Loc -> RegM freeRegs ()
forall freeRegs. RegMap Loc -> RegM freeRegs ()
setAssigR       RegMap Loc
assig


-- | Do allocation for a sequence of instructions.
linearRA
        :: (FR freeRegs, Outputable instr, Instruction instr)
        => BlockMap RegSet                      -- ^ map of what vregs are live on entry to each block.
        -> [instr]                              -- ^ accumulator for instructions already processed.
        -> [NatBasicBlock instr]                -- ^ accumulator for blocks of fixup code.
        -> BlockId                              -- ^ id of the current block, for debugging.
        -> [LiveInstr instr]                    -- ^ liveness annotated instructions in this block.

        -> RegM freeRegs
                ( [instr]                       --   instructions after register allocation
                , [NatBasicBlock instr])        --   fresh blocks of fixup code.


linearRA :: BlockMap RegSet
-> [instr]
-> [NatBasicBlock instr]
-> BlockId
-> [LiveInstr instr]
-> RegM freeRegs ([instr], [NatBasicBlock instr])
linearRA BlockMap RegSet
_          [instr]
accInstr [NatBasicBlock instr]
accFixup BlockId
_ []
        = ([instr], [NatBasicBlock instr])
-> RegM freeRegs ([instr], [NatBasicBlock instr])
forall (m :: * -> *) a. Monad m => a -> m a
return
                ( [instr] -> [instr]
forall a. [a] -> [a]
reverse [instr]
accInstr              -- instrs need to be returned in the correct order.
                , [NatBasicBlock instr]
accFixup)                     -- it doesn't matter what order the fixup blocks are returned in.


linearRA BlockMap RegSet
block_live [instr]
accInstr [NatBasicBlock instr]
accFixups BlockId
id (LiveInstr instr
instr:[LiveInstr instr]
instrs)
 = do
        ([instr]
accInstr', [NatBasicBlock instr]
new_fixups) <- BlockMap RegSet
-> [instr]
-> BlockId
-> LiveInstr instr
-> RegM freeRegs ([instr], [NatBasicBlock instr])
forall freeRegs instr.
(FR freeRegs, Outputable instr, Instruction instr) =>
BlockMap RegSet
-> [instr]
-> BlockId
-> LiveInstr instr
-> RegM freeRegs ([instr], [NatBasicBlock instr])
raInsn BlockMap RegSet
block_live [instr]
accInstr BlockId
id LiveInstr instr
instr

        BlockMap RegSet
-> [instr]
-> [NatBasicBlock instr]
-> BlockId
-> [LiveInstr instr]
-> RegM freeRegs ([instr], [NatBasicBlock instr])
forall freeRegs instr.
(FR freeRegs, Outputable instr, Instruction instr) =>
BlockMap RegSet
-> [instr]
-> [NatBasicBlock instr]
-> BlockId
-> [LiveInstr instr]
-> RegM freeRegs ([instr], [NatBasicBlock instr])
linearRA BlockMap RegSet
block_live [instr]
accInstr' ([NatBasicBlock instr]
new_fixups [NatBasicBlock instr]
-> [NatBasicBlock instr] -> [NatBasicBlock instr]
forall a. [a] -> [a] -> [a]
++ [NatBasicBlock instr]
accFixups) BlockId
id [LiveInstr instr]
instrs


-- | Do allocation for a single instruction.
raInsn
        :: (FR freeRegs, Outputable instr, Instruction instr)
        => BlockMap RegSet                      -- ^ map of what vregs are love on entry to each block.
        -> [instr]                              -- ^ accumulator for instructions already processed.
        -> BlockId                              -- ^ the id of the current block, for debugging
        -> LiveInstr instr                      -- ^ the instr to have its regs allocated, with liveness info.
        -> RegM freeRegs
                ( [instr]                       -- new instructions
                , [NatBasicBlock instr])        -- extra fixup blocks

raInsn :: BlockMap RegSet
-> [instr]
-> BlockId
-> LiveInstr instr
-> RegM freeRegs ([instr], [NatBasicBlock instr])
raInsn BlockMap RegSet
_     [instr]
new_instrs BlockId
_ (LiveInstr InstrSR instr
ii Maybe Liveness
Nothing)
        | Just Int
n        <- InstrSR instr -> Maybe Int
forall instr. Instruction instr => instr -> Maybe Int
takeDeltaInstr InstrSR instr
ii
        = do    Int -> RegM freeRegs ()
forall freeRegs. Int -> RegM freeRegs ()
setDeltaR Int
n
                ([instr], [NatBasicBlock instr])
-> RegM freeRegs ([instr], [NatBasicBlock instr])
forall (m :: * -> *) a. Monad m => a -> m a
return ([instr]
new_instrs, [])

raInsn BlockMap RegSet
_     [instr]
new_instrs BlockId
_ (LiveInstr ii :: InstrSR instr
ii@(Instr instr
i) Maybe Liveness
Nothing)
        | InstrSR instr -> Bool
forall instr. Instruction instr => instr -> Bool
isMetaInstr InstrSR instr
ii
        = ([instr], [NatBasicBlock instr])
-> RegM freeRegs ([instr], [NatBasicBlock instr])
forall (m :: * -> *) a. Monad m => a -> m a
return (instr
i instr -> [instr] -> [instr]
forall a. a -> [a] -> [a]
: [instr]
new_instrs, [])


raInsn BlockMap RegSet
block_live [instr]
new_instrs BlockId
id (LiveInstr (Instr instr
instr) (Just Liveness
live))
 = do
    RegMap Loc
assig    <- RegM freeRegs (RegMap Loc)
forall freeRegs. RegM freeRegs (RegMap Loc)
getAssigR

    -- If we have a reg->reg move between virtual registers, where the
    -- src register is not live after this instruction, and the dst
    -- register does not already have an assignment,
    -- and the source register is assigned to a register, not to a spill slot,
    -- then we can eliminate the instruction.
    -- (we can't eliminate it if the source register is on the stack, because
    --  we do not want to use one spill slot for different virtual registers)
    case instr -> Maybe (Reg, Reg)
forall instr. Instruction instr => instr -> Maybe (Reg, Reg)
takeRegRegMoveInstr instr
instr of
        Just (Reg
src,Reg
dst)  | Reg
src Reg -> RegSet -> Bool
forall a. Uniquable a => a -> UniqSet a -> Bool
`elementOfUniqSet` (Liveness -> RegSet
liveDieRead Liveness
live),
                          Reg -> Bool
isVirtualReg Reg
dst,
                          Bool -> Bool
not (Reg
dst Reg -> RegMap Loc -> Bool
forall key elt. Uniquable key => key -> UniqFM elt -> Bool
`elemUFM` RegMap Loc
assig),
                          Reg -> Bool
isRealReg Reg
src Bool -> Bool -> Bool
|| Reg -> RegMap Loc -> Bool
isInReg Reg
src RegMap Loc
assig -> do
           case Reg
src of
              (RegReal RealReg
rr) -> RegMap Loc -> RegM freeRegs ()
forall freeRegs. RegMap Loc -> RegM freeRegs ()
setAssigR (RegMap Loc -> Reg -> Loc -> RegMap Loc
forall key elt.
Uniquable key =>
UniqFM elt -> key -> elt -> UniqFM elt
addToUFM RegMap Loc
assig Reg
dst (RealReg -> Loc
InReg RealReg
rr))
                -- if src is a fixed reg, then we just map dest to this
                -- reg in the assignment.  src must be an allocatable reg,
                -- otherwise it wouldn't be in r_dying.
              Reg
_virt -> case RegMap Loc -> Reg -> Maybe Loc
forall key elt. Uniquable key => UniqFM elt -> key -> Maybe elt
lookupUFM RegMap Loc
assig Reg
src of
                         Maybe Loc
Nothing -> String -> RegM freeRegs ()
forall a. String -> a
panic String
"raInsn"
                         Just Loc
loc ->
                           RegMap Loc -> RegM freeRegs ()
forall freeRegs. RegMap Loc -> RegM freeRegs ()
setAssigR (RegMap Loc -> Reg -> Loc -> RegMap Loc
forall key elt.
Uniquable key =>
UniqFM elt -> key -> elt -> UniqFM elt
addToUFM (RegMap Loc -> Reg -> RegMap Loc
forall key elt. Uniquable key => UniqFM elt -> key -> UniqFM elt
delFromUFM RegMap Loc
assig Reg
src) Reg
dst Loc
loc)

           -- we have eliminated this instruction
          {-
          freeregs <- getFreeRegsR
          assig <- getAssigR
          pprTrace "raInsn" (text "ELIMINATED: " <> docToSDoc (pprInstr instr)
                        $$ ppr r_dying <+> ppr w_dying $$ text (show freeregs) $$ ppr assig) $ do
          -}
           ([instr], [NatBasicBlock instr])
-> RegM freeRegs ([instr], [NatBasicBlock instr])
forall (m :: * -> *) a. Monad m => a -> m a
return ([instr]
new_instrs, [])

        Maybe (Reg, Reg)
_ -> BlockMap RegSet
-> [instr]
-> BlockId
-> instr
-> [Reg]
-> [Reg]
-> RegM freeRegs ([instr], [NatBasicBlock instr])
forall freeRegs instr.
(FR freeRegs, Instruction instr, Outputable instr) =>
BlockMap RegSet
-> [instr]
-> BlockId
-> instr
-> [Reg]
-> [Reg]
-> RegM freeRegs ([instr], [NatBasicBlock instr])
genRaInsn BlockMap RegSet
block_live [instr]
new_instrs BlockId
id instr
instr
                        (RegSet -> [Reg]
forall elt. UniqSet elt -> [elt]
nonDetEltsUniqSet (RegSet -> [Reg]) -> RegSet -> [Reg]
forall a b. (a -> b) -> a -> b
$ Liveness -> RegSet
liveDieRead Liveness
live)
                        (RegSet -> [Reg]
forall elt. UniqSet elt -> [elt]
nonDetEltsUniqSet (RegSet -> [Reg]) -> RegSet -> [Reg]
forall a b. (a -> b) -> a -> b
$ Liveness -> RegSet
liveDieWrite Liveness
live)
                        -- See Note [Unique Determinism and code generation]

raInsn BlockMap RegSet
_ [instr]
_ BlockId
_ LiveInstr instr
instr
        = String -> SDoc -> RegM freeRegs ([instr], [NatBasicBlock instr])
forall a. HasCallStack => String -> SDoc -> a
pprPanic String
"raInsn" (String -> SDoc
text String
"no match for:" SDoc -> SDoc -> SDoc
<> LiveInstr instr -> SDoc
forall a. Outputable a => a -> SDoc
ppr LiveInstr instr
instr)

-- ToDo: what can we do about
--
--     R1 = x
--     jump I64[x] // [R1]
--
-- where x is mapped to the same reg as R1.  We want to coalesce x and
-- R1, but the register allocator doesn't know whether x will be
-- assigned to again later, in which case x and R1 should be in
-- different registers.  Right now we assume the worst, and the
-- assignment to R1 will clobber x, so we'll spill x into another reg,
-- generating another reg->reg move.


isInReg :: Reg -> RegMap Loc -> Bool
isInReg :: Reg -> RegMap Loc -> Bool
isInReg Reg
src RegMap Loc
assig | Just (InReg RealReg
_) <- RegMap Loc -> Reg -> Maybe Loc
forall key elt. Uniquable key => UniqFM elt -> key -> Maybe elt
lookupUFM RegMap Loc
assig Reg
src = Bool
True
                  | Bool
otherwise = Bool
False


genRaInsn :: (FR freeRegs, Instruction instr, Outputable instr)
          => BlockMap RegSet
          -> [instr]
          -> BlockId
          -> instr
          -> [Reg]
          -> [Reg]
          -> RegM freeRegs ([instr], [NatBasicBlock instr])

genRaInsn :: BlockMap RegSet
-> [instr]
-> BlockId
-> instr
-> [Reg]
-> [Reg]
-> RegM freeRegs ([instr], [NatBasicBlock instr])
genRaInsn BlockMap RegSet
block_live [instr]
new_instrs BlockId
block_id instr
instr [Reg]
r_dying [Reg]
w_dying = do
  DynFlags
dflags <- RegM freeRegs DynFlags
forall (m :: * -> *). HasDynFlags m => m DynFlags
getDynFlags
  let platform :: Platform
platform = DynFlags -> Platform
targetPlatform DynFlags
dflags
  case Platform -> instr -> RegUsage
forall instr. Instruction instr => Platform -> instr -> RegUsage
regUsageOfInstr Platform
platform instr
instr of { RU [Reg]
read [Reg]
written ->
    do
    let real_written :: [RealReg]
real_written    = [ RealReg
rr  | (RegReal     RealReg
rr) <- [Reg]
written ]
    let virt_written :: [VirtualReg]
virt_written    = [ VirtualReg
vr  | (RegVirtual  VirtualReg
vr) <- [Reg]
written ]

    -- we don't need to do anything with real registers that are
    -- only read by this instr.  (the list is typically ~2 elements,
    -- so using nub isn't a problem).
    let virt_read :: [VirtualReg]
virt_read       = [VirtualReg] -> [VirtualReg]
forall a. Eq a => [a] -> [a]
nub [ VirtualReg
vr      | (RegVirtual VirtualReg
vr) <- [Reg]
read ]

    -- debugging
{-    freeregs <- getFreeRegsR
    assig    <- getAssigR
    pprDebugAndThen (defaultDynFlags Settings{ sTargetPlatform=platform } undefined) trace "genRaInsn"
        (ppr instr
                $$ text "r_dying      = " <+> ppr r_dying
                $$ text "w_dying      = " <+> ppr w_dying
                $$ text "virt_read    = " <+> ppr virt_read
                $$ text "virt_written = " <+> ppr virt_written
                $$ text "freeregs     = " <+> text (show freeregs)
                $$ text "assig        = " <+> ppr assig)
        $ do
-}

    -- (a), (b) allocate real regs for all regs read by this instruction.
    ([instr]
r_spills, [RealReg]
r_allocd) <-
        Bool
-> [VirtualReg]
-> [instr]
-> [RealReg]
-> [VirtualReg]
-> RegM freeRegs ([instr], [RealReg])
forall freeRegs instr.
(FR freeRegs, Outputable instr, Instruction instr) =>
Bool
-> [VirtualReg]
-> [instr]
-> [RealReg]
-> [VirtualReg]
-> RegM freeRegs ([instr], [RealReg])
allocateRegsAndSpill Bool
True{-reading-} [VirtualReg]
virt_read [] [] [VirtualReg]
virt_read

    -- (c) save any temporaries which will be clobbered by this instruction
    [instr]
clobber_saves <- [RealReg] -> [Reg] -> RegM freeRegs [instr]
forall instr freeRegs.
(Instruction instr, FR freeRegs) =>
[RealReg] -> [Reg] -> RegM freeRegs [instr]
saveClobberedTemps [RealReg]
real_written [Reg]
r_dying

    -- (d) Update block map for new destinations
    -- NB. do this before removing dead regs from the assignment, because
    -- these dead regs might in fact be live in the jump targets (they're
    -- only dead in the code that follows in the current basic block).
    ([NatBasicBlock instr]
fixup_blocks, instr
adjusted_instr)
        <- BlockMap RegSet
-> BlockId -> instr -> RegM freeRegs ([NatBasicBlock instr], instr)
forall freeRegs instr.
(FR freeRegs, Instruction instr, Outputable instr) =>
BlockMap RegSet
-> BlockId -> instr -> RegM freeRegs ([NatBasicBlock instr], instr)
joinToTargets BlockMap RegSet
block_live BlockId
block_id instr
instr

    -- Debugging - show places where the reg alloc inserted
    -- assignment fixup blocks.
    -- when (not $ null fixup_blocks) $
    --    pprTrace "fixup_blocks" (ppr fixup_blocks) (return ())

    -- (e) Delete all register assignments for temps which are read
    --     (only) and die here.  Update the free register list.
    [Reg] -> RegM freeRegs ()
forall freeRegs. FR freeRegs => [Reg] -> RegM freeRegs ()
releaseRegs [Reg]
r_dying

    -- (f) Mark regs which are clobbered as unallocatable
    [RealReg] -> RegM freeRegs ()
forall freeRegs. FR freeRegs => [RealReg] -> RegM freeRegs ()
clobberRegs [RealReg]
real_written

    -- (g) Allocate registers for temporaries *written* (only)
    ([instr]
w_spills, [RealReg]
w_allocd) <-
        Bool
-> [VirtualReg]
-> [instr]
-> [RealReg]
-> [VirtualReg]
-> RegM freeRegs ([instr], [RealReg])
forall freeRegs instr.
(FR freeRegs, Outputable instr, Instruction instr) =>
Bool
-> [VirtualReg]
-> [instr]
-> [RealReg]
-> [VirtualReg]
-> RegM freeRegs ([instr], [RealReg])
allocateRegsAndSpill Bool
False{-writing-} [VirtualReg]
virt_written [] [] [VirtualReg]
virt_written

    -- (h) Release registers for temps which are written here and not
    -- used again.
    [Reg] -> RegM freeRegs ()
forall freeRegs. FR freeRegs => [Reg] -> RegM freeRegs ()
releaseRegs [Reg]
w_dying

    let
        -- (i) Patch the instruction
        patch_map :: UniqFM Reg
patch_map
                = [(VirtualReg, Reg)] -> UniqFM Reg
forall key elt. Uniquable key => [(key, elt)] -> UniqFM elt
listToUFM
                        [ (VirtualReg
t, RealReg -> Reg
RegReal RealReg
r)
                                | (VirtualReg
t, RealReg
r) <- [VirtualReg] -> [RealReg] -> [(VirtualReg, RealReg)]
forall a b. [a] -> [b] -> [(a, b)]
zip [VirtualReg]
virt_read    [RealReg]
r_allocd
                                         [(VirtualReg, RealReg)]
-> [(VirtualReg, RealReg)] -> [(VirtualReg, RealReg)]
forall a. [a] -> [a] -> [a]
++ [VirtualReg] -> [RealReg] -> [(VirtualReg, RealReg)]
forall a b. [a] -> [b] -> [(a, b)]
zip [VirtualReg]
virt_written [RealReg]
w_allocd ]

        patched_instr :: instr
patched_instr
                = instr -> (Reg -> Reg) -> instr
forall instr. Instruction instr => instr -> (Reg -> Reg) -> instr
patchRegsOfInstr instr
adjusted_instr Reg -> Reg
patchLookup

        patchLookup :: Reg -> Reg
patchLookup Reg
x
                = case UniqFM Reg -> Reg -> Maybe Reg
forall key elt. Uniquable key => UniqFM elt -> key -> Maybe elt
lookupUFM UniqFM Reg
patch_map Reg
x of
                        Maybe Reg
Nothing -> Reg
x
                        Just Reg
y  -> Reg
y


    -- (j) free up stack slots for dead spilled regs
    -- TODO (can't be bothered right now)

    -- erase reg->reg moves where the source and destination are the same.
    --  If the src temp didn't die in this instr but happened to be allocated
    --  to the same real reg as the destination, then we can erase the move anyway.
    let squashed_instr :: [instr]
squashed_instr  = case instr -> Maybe (Reg, Reg)
forall instr. Instruction instr => instr -> Maybe (Reg, Reg)
takeRegRegMoveInstr instr
patched_instr of
                                Just (Reg
src, Reg
dst)
                                 | Reg
src Reg -> Reg -> Bool
forall a. Eq a => a -> a -> Bool
== Reg
dst   -> []
                                Maybe (Reg, Reg)
_               -> [instr
patched_instr]

    let code :: [instr]
code = [instr]
squashed_instr [instr] -> [instr] -> [instr]
forall a. [a] -> [a] -> [a]
++ [instr]
w_spills [instr] -> [instr] -> [instr]
forall a. [a] -> [a] -> [a]
++ [instr] -> [instr]
forall a. [a] -> [a]
reverse [instr]
r_spills
                [instr] -> [instr] -> [instr]
forall a. [a] -> [a] -> [a]
++ [instr]
clobber_saves [instr] -> [instr] -> [instr]
forall a. [a] -> [a] -> [a]
++ [instr]
new_instrs

--    pprTrace "patched-code" ((vcat $ map (docToSDoc . pprInstr) code)) $ do
--    pprTrace "pached-fixup" ((ppr fixup_blocks)) $ do

    ([instr], [NatBasicBlock instr])
-> RegM freeRegs ([instr], [NatBasicBlock instr])
forall (m :: * -> *) a. Monad m => a -> m a
return ([instr]
code, [NatBasicBlock instr]
fixup_blocks)

  }

-- -----------------------------------------------------------------------------
-- releaseRegs

releaseRegs :: FR freeRegs => [Reg] -> RegM freeRegs ()
releaseRegs :: [Reg] -> RegM freeRegs ()
releaseRegs [Reg]
regs = do
  DynFlags
dflags <- RegM freeRegs DynFlags
forall (m :: * -> *). HasDynFlags m => m DynFlags
getDynFlags
  let platform :: Platform
platform = DynFlags -> Platform
targetPlatform DynFlags
dflags
  RegMap Loc
assig <- RegM freeRegs (RegMap Loc)
forall freeRegs. RegM freeRegs (RegMap Loc)
getAssigR
  freeRegs
free <- RegM freeRegs freeRegs
forall freeRegs. RegM freeRegs freeRegs
getFreeRegsR
  let loop :: RegMap Loc -> freeRegs -> [Reg] -> RegM freeRegs ()
loop RegMap Loc
assig !freeRegs
free [] = do RegMap Loc -> RegM freeRegs ()
forall freeRegs. RegMap Loc -> RegM freeRegs ()
setAssigR RegMap Loc
assig; freeRegs -> RegM freeRegs ()
forall freeRegs. freeRegs -> RegM freeRegs ()
setFreeRegsR freeRegs
free; () -> RegM freeRegs ()
forall (m :: * -> *) a. Monad m => a -> m a
return ()
      loop RegMap Loc
assig !freeRegs
free (RegReal RealReg
rr : [Reg]
rs) = RegMap Loc -> freeRegs -> [Reg] -> RegM freeRegs ()
loop RegMap Loc
assig (Platform -> RealReg -> freeRegs -> freeRegs
forall freeRegs.
FR freeRegs =>
Platform -> RealReg -> freeRegs -> freeRegs
frReleaseReg Platform
platform RealReg
rr freeRegs
free) [Reg]
rs
      loop RegMap Loc
assig !freeRegs
free (Reg
r:[Reg]
rs) =
         case RegMap Loc -> Reg -> Maybe Loc
forall key elt. Uniquable key => UniqFM elt -> key -> Maybe elt
lookupUFM RegMap Loc
assig Reg
r of
         Just (InBoth RealReg
real Int
_) -> RegMap Loc -> freeRegs -> [Reg] -> RegM freeRegs ()
loop (RegMap Loc -> Reg -> RegMap Loc
forall key elt. Uniquable key => UniqFM elt -> key -> UniqFM elt
delFromUFM RegMap Loc
assig Reg
r)
                                      (Platform -> RealReg -> freeRegs -> freeRegs
forall freeRegs.
FR freeRegs =>
Platform -> RealReg -> freeRegs -> freeRegs
frReleaseReg Platform
platform RealReg
real freeRegs
free) [Reg]
rs
         Just (InReg RealReg
real)    -> RegMap Loc -> freeRegs -> [Reg] -> RegM freeRegs ()
loop (RegMap Loc -> Reg -> RegMap Loc
forall key elt. Uniquable key => UniqFM elt -> key -> UniqFM elt
delFromUFM RegMap Loc
assig Reg
r)
                                      (Platform -> RealReg -> freeRegs -> freeRegs
forall freeRegs.
FR freeRegs =>
Platform -> RealReg -> freeRegs -> freeRegs
frReleaseReg Platform
platform RealReg
real freeRegs
free) [Reg]
rs
         Maybe Loc
_                    -> RegMap Loc -> freeRegs -> [Reg] -> RegM freeRegs ()
loop (RegMap Loc -> Reg -> RegMap Loc
forall key elt. Uniquable key => UniqFM elt -> key -> UniqFM elt
delFromUFM RegMap Loc
assig Reg
r) freeRegs
free [Reg]
rs
  RegMap Loc -> freeRegs -> [Reg] -> RegM freeRegs ()
forall freeRegs.
FR freeRegs =>
RegMap Loc -> freeRegs -> [Reg] -> RegM freeRegs ()
loop RegMap Loc
assig freeRegs
free [Reg]
regs


-- -----------------------------------------------------------------------------
-- Clobber real registers

-- For each temp in a register that is going to be clobbered:
--      - if the temp dies after this instruction, do nothing
--      - otherwise, put it somewhere safe (another reg if possible,
--              otherwise spill and record InBoth in the assignment).
--      - for allocateRegs on the temps *read*,
--      - clobbered regs are allocatable.
--
--      for allocateRegs on the temps *written*,
--        - clobbered regs are not allocatable.
--

saveClobberedTemps
        :: (Instruction instr, FR freeRegs)
        => [RealReg]            -- real registers clobbered by this instruction
        -> [Reg]                -- registers which are no longer live after this insn
        -> RegM freeRegs [instr]         -- return: instructions to spill any temps that will
                                -- be clobbered.

saveClobberedTemps :: [RealReg] -> [Reg] -> RegM freeRegs [instr]
saveClobberedTemps [] [Reg]
_
        = [instr] -> RegM freeRegs [instr]
forall (m :: * -> *) a. Monad m => a -> m a
return []

saveClobberedTemps [RealReg]
clobbered [Reg]
dying
 = do
        RegMap Loc
assig   <- RegM freeRegs (RegMap Loc)
forall freeRegs. RegM freeRegs (RegMap Loc)
getAssigR
        let to_spill :: [(Unique, RealReg)]
to_spill
                = [ (Unique
temp,RealReg
reg)
                        | (Unique
temp, InReg RealReg
reg) <- RegMap Loc -> [(Unique, Loc)]
forall elt. UniqFM elt -> [(Unique, elt)]
nonDetUFMToList RegMap Loc
assig
                        -- This is non-deterministic but we do not
                        -- currently support deterministic code-generation.
                        -- See Note [Unique Determinism and code generation]
                        , (RealReg -> Bool) -> [RealReg] -> Bool
forall (t :: * -> *) a. Foldable t => (a -> Bool) -> t a -> Bool
any (RealReg -> RealReg -> Bool
realRegsAlias RealReg
reg) [RealReg]
clobbered
                        , Unique
temp Unique -> [Unique] -> Bool
forall (t :: * -> *) a. (Foldable t, Eq a) => a -> t a -> Bool
`notElem` (Reg -> Unique) -> [Reg] -> [Unique]
forall a b. (a -> b) -> [a] -> [b]
map Reg -> Unique
forall a. Uniquable a => a -> Unique
getUnique [Reg]
dying  ]

        ([instr]
instrs,RegMap Loc
assig') <- RegMap Loc
-> [instr]
-> [(Unique, RealReg)]
-> RegM freeRegs ([instr], RegMap Loc)
forall freeRegs a.
(FR freeRegs, Instruction a) =>
RegMap Loc
-> [a] -> [(Unique, RealReg)] -> RegM freeRegs ([a], RegMap Loc)
clobber RegMap Loc
assig [] [(Unique, RealReg)]
to_spill
        RegMap Loc -> RegM freeRegs ()
forall freeRegs. RegMap Loc -> RegM freeRegs ()
setAssigR RegMap Loc
assig'
        [instr] -> RegM freeRegs [instr]
forall (m :: * -> *) a. Monad m => a -> m a
return [instr]
instrs

   where
     clobber :: RegMap Loc
-> [a] -> [(Unique, RealReg)] -> RegM freeRegs ([a], RegMap Loc)
clobber RegMap Loc
assig [a]
instrs []
            = ([a], RegMap Loc) -> RegM freeRegs ([a], RegMap Loc)
forall (m :: * -> *) a. Monad m => a -> m a
return ([a]
instrs, RegMap Loc
assig)

     clobber RegMap Loc
assig [a]
instrs ((Unique
temp, RealReg
reg) : [(Unique, RealReg)]
rest)
       = do DynFlags
dflags <- RegM freeRegs DynFlags
forall (m :: * -> *). HasDynFlags m => m DynFlags
getDynFlags
            let platform :: Platform
platform = DynFlags -> Platform
targetPlatform DynFlags
dflags

            freeRegs
freeRegs <- RegM freeRegs freeRegs
forall freeRegs. RegM freeRegs freeRegs
getFreeRegsR
            let regclass :: RegClass
regclass = Platform -> RealReg -> RegClass
targetClassOfRealReg Platform
platform RealReg
reg
                freeRegs_thisClass :: [RealReg]
freeRegs_thisClass = Platform -> RegClass -> freeRegs -> [RealReg]
forall freeRegs.
FR freeRegs =>
Platform -> RegClass -> freeRegs -> [RealReg]
frGetFreeRegs Platform
platform RegClass
regclass freeRegs
freeRegs

            case (RealReg -> Bool) -> [RealReg] -> [RealReg]
forall a. (a -> Bool) -> [a] -> [a]
filter (RealReg -> [RealReg] -> Bool
forall (t :: * -> *) a. (Foldable t, Eq a) => a -> t a -> Bool
`notElem` [RealReg]
clobbered) [RealReg]
freeRegs_thisClass of

              -- (1) we have a free reg of the right class that isn't
              -- clobbered by this instruction; use it to save the
              -- clobbered value.
              (RealReg
my_reg : [RealReg]
_) -> do
                  freeRegs -> RegM freeRegs ()
forall freeRegs. freeRegs -> RegM freeRegs ()
setFreeRegsR (Platform -> RealReg -> freeRegs -> freeRegs
forall freeRegs.
FR freeRegs =>
Platform -> RealReg -> freeRegs -> freeRegs
frAllocateReg Platform
platform RealReg
my_reg freeRegs
freeRegs)

                  let new_assign :: RegMap Loc
new_assign = RegMap Loc -> Unique -> Loc -> RegMap Loc
forall key elt.
Uniquable key =>
UniqFM elt -> key -> elt -> UniqFM elt
addToUFM RegMap Loc
assig Unique
temp (RealReg -> Loc
InReg RealReg
my_reg)
                  let instr :: a
instr = Platform -> Reg -> Reg -> a
forall instr. Instruction instr => Platform -> Reg -> Reg -> instr
mkRegRegMoveInstr Platform
platform
                                  (RealReg -> Reg
RegReal RealReg
reg) (RealReg -> Reg
RegReal RealReg
my_reg)

                  RegMap Loc
-> [a] -> [(Unique, RealReg)] -> RegM freeRegs ([a], RegMap Loc)
clobber RegMap Loc
new_assign (a
instr a -> [a] -> [a]
forall a. a -> [a] -> [a]
: [a]
instrs) [(Unique, RealReg)]
rest

              -- (2) no free registers: spill the value
              [] -> do
                  (a
spill, Int
slot)   <- Reg -> Unique -> RegM freeRegs (a, Int)
forall instr freeRegs.
Instruction instr =>
Reg -> Unique -> RegM freeRegs (instr, Int)
spillR (RealReg -> Reg
RegReal RealReg
reg) Unique
temp

                  -- record why this reg was spilled for profiling
                  SpillReason -> RegM freeRegs ()
forall freeRegs. SpillReason -> RegM freeRegs ()
recordSpill (Unique -> SpillReason
SpillClobber Unique
temp)

                  let new_assign :: RegMap Loc
new_assign  = RegMap Loc -> Unique -> Loc -> RegMap Loc
forall key elt.
Uniquable key =>
UniqFM elt -> key -> elt -> UniqFM elt
addToUFM RegMap Loc
assig Unique
temp (RealReg -> Int -> Loc
InBoth RealReg
reg Int
slot)

                  RegMap Loc
-> [a] -> [(Unique, RealReg)] -> RegM freeRegs ([a], RegMap Loc)
clobber RegMap Loc
new_assign (a
spill a -> [a] -> [a]
forall a. a -> [a] -> [a]
: [a]
instrs) [(Unique, RealReg)]
rest



-- | Mark all these real regs as allocated,
--      and kick out their vreg assignments.
--
clobberRegs :: FR freeRegs => [RealReg] -> RegM freeRegs ()
clobberRegs :: [RealReg] -> RegM freeRegs ()
clobberRegs []
        = () -> RegM freeRegs ()
forall (m :: * -> *) a. Monad m => a -> m a
return ()

clobberRegs [RealReg]
clobbered
 = do   DynFlags
dflags <- RegM freeRegs DynFlags
forall (m :: * -> *). HasDynFlags m => m DynFlags
getDynFlags
        let platform :: Platform
platform = DynFlags -> Platform
targetPlatform DynFlags
dflags

        freeRegs
freeregs        <- RegM freeRegs freeRegs
forall freeRegs. RegM freeRegs freeRegs
getFreeRegsR
        freeRegs -> RegM freeRegs ()
forall freeRegs. freeRegs -> RegM freeRegs ()
setFreeRegsR (freeRegs -> RegM freeRegs ()) -> freeRegs -> RegM freeRegs ()
forall a b. (a -> b) -> a -> b
$! (freeRegs -> RealReg -> freeRegs)
-> freeRegs -> [RealReg] -> freeRegs
forall (t :: * -> *) b a.
Foldable t =>
(b -> a -> b) -> b -> t a -> b
foldl' ((RealReg -> freeRegs -> freeRegs)
-> freeRegs -> RealReg -> freeRegs
forall a b c. (a -> b -> c) -> b -> a -> c
flip ((RealReg -> freeRegs -> freeRegs)
 -> freeRegs -> RealReg -> freeRegs)
-> (RealReg -> freeRegs -> freeRegs)
-> freeRegs
-> RealReg
-> freeRegs
forall a b. (a -> b) -> a -> b
$ Platform -> RealReg -> freeRegs -> freeRegs
forall freeRegs.
FR freeRegs =>
Platform -> RealReg -> freeRegs -> freeRegs
frAllocateReg Platform
platform) freeRegs
freeregs [RealReg]
clobbered

        RegMap Loc
assig           <- RegM freeRegs (RegMap Loc)
forall freeRegs. RegM freeRegs (RegMap Loc)
getAssigR
        RegMap Loc -> RegM freeRegs ()
forall freeRegs. RegMap Loc -> RegM freeRegs ()
setAssigR (RegMap Loc -> RegM freeRegs ()) -> RegMap Loc -> RegM freeRegs ()
forall a b. (a -> b) -> a -> b
$! RegMap Loc -> [(Unique, Loc)] -> RegMap Loc
forall key.
Uniquable key =>
RegMap Loc -> [(key, Loc)] -> RegMap Loc
clobber RegMap Loc
assig (RegMap Loc -> [(Unique, Loc)]
forall elt. UniqFM elt -> [(Unique, elt)]
nonDetUFMToList RegMap Loc
assig)
          -- This is non-deterministic but we do not
          -- currently support deterministic code-generation.
          -- See Note [Unique Determinism and code generation]

   where
        -- if the temp was InReg and clobbered, then we will have
        -- saved it in saveClobberedTemps above.  So the only case
        -- we have to worry about here is InBoth.  Note that this
        -- also catches temps which were loaded up during allocation
        -- of read registers, not just those saved in saveClobberedTemps.

        clobber :: RegMap Loc -> [(key, Loc)] -> RegMap Loc
clobber RegMap Loc
assig []
                = RegMap Loc
assig

        clobber RegMap Loc
assig ((key
temp, InBoth RealReg
reg Int
slot) : [(key, Loc)]
rest)
                | (RealReg -> Bool) -> [RealReg] -> Bool
forall (t :: * -> *) a. Foldable t => (a -> Bool) -> t a -> Bool
any (RealReg -> RealReg -> Bool
realRegsAlias RealReg
reg) [RealReg]
clobbered
                = RegMap Loc -> [(key, Loc)] -> RegMap Loc
clobber (RegMap Loc -> key -> Loc -> RegMap Loc
forall key elt.
Uniquable key =>
UniqFM elt -> key -> elt -> UniqFM elt
addToUFM RegMap Loc
assig key
temp (Int -> Loc
InMem Int
slot)) [(key, Loc)]
rest

        clobber RegMap Loc
assig ((key, Loc)
_:[(key, Loc)]
rest)
                = RegMap Loc -> [(key, Loc)] -> RegMap Loc
clobber RegMap Loc
assig [(key, Loc)]
rest

-- -----------------------------------------------------------------------------
-- allocateRegsAndSpill

-- Why are we performing a spill?
data SpillLoc = ReadMem StackSlot  -- reading from register only in memory
              | WriteNew           -- writing to a new variable
              | WriteMem           -- writing to register only in memory
-- Note that ReadNew is not valid, since you don't want to be reading
-- from an uninitialized register.  We also don't need the location of
-- the register in memory, since that will be invalidated by the write.
-- Technically, we could coalesce WriteNew and WriteMem into a single
-- entry as well. -- EZY

-- This function does several things:
--   For each temporary referred to by this instruction,
--   we allocate a real register (spilling another temporary if necessary).
--   We load the temporary up from memory if necessary.
--   We also update the register assignment in the process, and
--   the list of free registers and free stack slots.

allocateRegsAndSpill
        :: (FR freeRegs, Outputable instr, Instruction instr)
        => Bool                 -- True <=> reading (load up spilled regs)
        -> [VirtualReg]         -- don't push these out
        -> [instr]              -- spill insns
        -> [RealReg]            -- real registers allocated (accum.)
        -> [VirtualReg]         -- temps to allocate
        -> RegM freeRegs ( [instr] , [RealReg])

allocateRegsAndSpill :: Bool
-> [VirtualReg]
-> [instr]
-> [RealReg]
-> [VirtualReg]
-> RegM freeRegs ([instr], [RealReg])
allocateRegsAndSpill Bool
_       [VirtualReg]
_    [instr]
spills [RealReg]
alloc []
        = ([instr], [RealReg]) -> RegM freeRegs ([instr], [RealReg])
forall (m :: * -> *) a. Monad m => a -> m a
return ([instr]
spills, [RealReg] -> [RealReg]
forall a. [a] -> [a]
reverse [RealReg]
alloc)

allocateRegsAndSpill Bool
reading [VirtualReg]
keep [instr]
spills [RealReg]
alloc (VirtualReg
r:[VirtualReg]
rs)
 = do   RegMap Loc
assig <- RegM freeRegs (RegMap Loc)
forall freeRegs. RegM freeRegs (RegMap Loc)
getAssigR
        let doSpill :: SpillLoc -> RegM freeRegs ([instr], [RealReg])
doSpill = Bool
-> [VirtualReg]
-> [instr]
-> [RealReg]
-> VirtualReg
-> [VirtualReg]
-> RegMap Loc
-> SpillLoc
-> RegM freeRegs ([instr], [RealReg])
forall freeRegs instr.
(FR freeRegs, Instruction instr, Outputable instr) =>
Bool
-> [VirtualReg]
-> [instr]
-> [RealReg]
-> VirtualReg
-> [VirtualReg]
-> RegMap Loc
-> SpillLoc
-> RegM freeRegs ([instr], [RealReg])
allocRegsAndSpill_spill Bool
reading [VirtualReg]
keep [instr]
spills [RealReg]
alloc VirtualReg
r [VirtualReg]
rs RegMap Loc
assig
        case RegMap Loc -> VirtualReg -> Maybe Loc
forall key elt. Uniquable key => UniqFM elt -> key -> Maybe elt
lookupUFM RegMap Loc
assig VirtualReg
r of
                -- case (1a): already in a register
                Just (InReg RealReg
my_reg) ->
                        Bool
-> [VirtualReg]
-> [instr]
-> [RealReg]
-> [VirtualReg]
-> RegM freeRegs ([instr], [RealReg])
forall freeRegs instr.
(FR freeRegs, Outputable instr, Instruction instr) =>
Bool
-> [VirtualReg]
-> [instr]
-> [RealReg]
-> [VirtualReg]
-> RegM freeRegs ([instr], [RealReg])
allocateRegsAndSpill Bool
reading [VirtualReg]
keep [instr]
spills (RealReg
my_regRealReg -> [RealReg] -> [RealReg]
forall a. a -> [a] -> [a]
:[RealReg]
alloc) [VirtualReg]
rs

                -- case (1b): already in a register (and memory)
                -- NB1. if we're writing this register, update its assignment to be
                -- InReg, because the memory value is no longer valid.
                -- NB2. This is why we must process written registers here, even if they
                -- are also read by the same instruction.
                Just (InBoth RealReg
my_reg Int
_)
                 -> do  Bool -> RegM freeRegs () -> RegM freeRegs ()
forall (f :: * -> *). Applicative f => Bool -> f () -> f ()
when (Bool -> Bool
not Bool
reading) (RegMap Loc -> RegM freeRegs ()
forall freeRegs. RegMap Loc -> RegM freeRegs ()
setAssigR (RegMap Loc -> VirtualReg -> Loc -> RegMap Loc
forall key elt.
Uniquable key =>
UniqFM elt -> key -> elt -> UniqFM elt
addToUFM RegMap Loc
assig VirtualReg
r (RealReg -> Loc
InReg RealReg
my_reg)))
                        Bool
-> [VirtualReg]
-> [instr]
-> [RealReg]
-> [VirtualReg]
-> RegM freeRegs ([instr], [RealReg])
forall freeRegs instr.
(FR freeRegs, Outputable instr, Instruction instr) =>
Bool
-> [VirtualReg]
-> [instr]
-> [RealReg]
-> [VirtualReg]
-> RegM freeRegs ([instr], [RealReg])
allocateRegsAndSpill Bool
reading [VirtualReg]
keep [instr]
spills (RealReg
my_regRealReg -> [RealReg] -> [RealReg]
forall a. a -> [a] -> [a]
:[RealReg]
alloc) [VirtualReg]
rs

                -- Not already in a register, so we need to find a free one...
                Just (InMem Int
slot) | Bool
reading   -> SpillLoc -> RegM freeRegs ([instr], [RealReg])
doSpill (Int -> SpillLoc
ReadMem Int
slot)
                                  | Bool
otherwise -> SpillLoc -> RegM freeRegs ([instr], [RealReg])
doSpill SpillLoc
WriteMem
                Maybe Loc
Nothing | Bool
reading   ->
                   String -> SDoc -> RegM freeRegs ([instr], [RealReg])
forall a. HasCallStack => String -> SDoc -> a
pprPanic String
"allocateRegsAndSpill: Cannot read from uninitialized register" (VirtualReg -> SDoc
forall a. Outputable a => a -> SDoc
ppr VirtualReg
r)
                   -- NOTE: if the input to the NCG contains some
                   -- unreachable blocks with junk code, this panic
                   -- might be triggered.  Make sure you only feed
                   -- sensible code into the NCG.  In CmmPipeline we
                   -- call removeUnreachableBlocks at the end for this
                   -- reason.

                        | Bool
otherwise -> SpillLoc -> RegM freeRegs ([instr], [RealReg])
doSpill SpillLoc
WriteNew


-- reading is redundant with reason, but we keep it around because it's
-- convenient and it maintains the recursive structure of the allocator. -- EZY
allocRegsAndSpill_spill :: (FR freeRegs, Instruction instr, Outputable instr)
                        => Bool
                        -> [VirtualReg]
                        -> [instr]
                        -> [RealReg]
                        -> VirtualReg
                        -> [VirtualReg]
                        -> UniqFM Loc
                        -> SpillLoc
                        -> RegM freeRegs ([instr], [RealReg])
allocRegsAndSpill_spill :: Bool
-> [VirtualReg]
-> [instr]
-> [RealReg]
-> VirtualReg
-> [VirtualReg]
-> RegMap Loc
-> SpillLoc
-> RegM freeRegs ([instr], [RealReg])
allocRegsAndSpill_spill Bool
reading [VirtualReg]
keep [instr]
spills [RealReg]
alloc VirtualReg
r [VirtualReg]
rs RegMap Loc
assig SpillLoc
spill_loc
 = do   DynFlags
dflags <- RegM freeRegs DynFlags
forall (m :: * -> *). HasDynFlags m => m DynFlags
getDynFlags
        let platform :: Platform
platform = DynFlags -> Platform
targetPlatform DynFlags
dflags
        freeRegs
freeRegs                <- RegM freeRegs freeRegs
forall freeRegs. RegM freeRegs freeRegs
getFreeRegsR
        let freeRegs_thisClass :: [RealReg]
freeRegs_thisClass  = Platform -> RegClass -> freeRegs -> [RealReg]
forall freeRegs.
FR freeRegs =>
Platform -> RegClass -> freeRegs -> [RealReg]
frGetFreeRegs Platform
platform (VirtualReg -> RegClass
classOfVirtualReg VirtualReg
r) freeRegs
freeRegs

        case [RealReg]
freeRegs_thisClass of

         -- case (2): we have a free register
         (RealReg
my_reg : [RealReg]
_) ->
           do   [instr]
spills'   <- VirtualReg
-> SpillLoc -> RealReg -> [instr] -> RegM freeRegs [instr]
forall instr freeRegs.
Instruction instr =>
VirtualReg
-> SpillLoc -> RealReg -> [instr] -> RegM freeRegs [instr]
loadTemp VirtualReg
r SpillLoc
spill_loc RealReg
my_reg [instr]
spills

                RegMap Loc -> RegM freeRegs ()
forall freeRegs. RegMap Loc -> RegM freeRegs ()
setAssigR       (RegMap Loc -> VirtualReg -> Loc -> RegMap Loc
forall key elt.
Uniquable key =>
UniqFM elt -> key -> elt -> UniqFM elt
addToUFM RegMap Loc
assig VirtualReg
r (Loc -> RegMap Loc) -> Loc -> RegMap Loc
forall a b. (a -> b) -> a -> b
$! SpillLoc -> RealReg -> Loc
newLocation SpillLoc
spill_loc RealReg
my_reg)
                freeRegs -> RegM freeRegs ()
forall freeRegs. freeRegs -> RegM freeRegs ()
setFreeRegsR (freeRegs -> RegM freeRegs ()) -> freeRegs -> RegM freeRegs ()
forall a b. (a -> b) -> a -> b
$  Platform -> RealReg -> freeRegs -> freeRegs
forall freeRegs.
FR freeRegs =>
Platform -> RealReg -> freeRegs -> freeRegs
frAllocateReg Platform
platform RealReg
my_reg freeRegs
freeRegs

                Bool
-> [VirtualReg]
-> [instr]
-> [RealReg]
-> [VirtualReg]
-> RegM freeRegs ([instr], [RealReg])
forall freeRegs instr.
(FR freeRegs, Outputable instr, Instruction instr) =>
Bool
-> [VirtualReg]
-> [instr]
-> [RealReg]
-> [VirtualReg]
-> RegM freeRegs ([instr], [RealReg])
allocateRegsAndSpill Bool
reading [VirtualReg]
keep [instr]
spills' (RealReg
my_reg RealReg -> [RealReg] -> [RealReg]
forall a. a -> [a] -> [a]
: [RealReg]
alloc) [VirtualReg]
rs


          -- case (3): we need to push something out to free up a register
         [] ->
           do   let inRegOrBoth :: Loc -> Bool
inRegOrBoth (InReg RealReg
_) = Bool
True
                    inRegOrBoth (InBoth RealReg
_ Int
_) = Bool
True
                    inRegOrBoth Loc
_ = Bool
False
                let candidates' :: RegMap Loc
candidates' =
                      (RegMap Loc -> [VirtualReg] -> RegMap Loc)
-> [VirtualReg] -> RegMap Loc -> RegMap Loc
forall a b c. (a -> b -> c) -> b -> a -> c
flip RegMap Loc -> [VirtualReg] -> RegMap Loc
forall key elt. Uniquable key => UniqFM elt -> [key] -> UniqFM elt
delListFromUFM [VirtualReg]
keep (RegMap Loc -> RegMap Loc) -> RegMap Loc -> RegMap Loc
forall a b. (a -> b) -> a -> b
$
                      (Loc -> Bool) -> RegMap Loc -> RegMap Loc
forall elt. (elt -> Bool) -> UniqFM elt -> UniqFM elt
filterUFM Loc -> Bool
inRegOrBoth (RegMap Loc -> RegMap Loc) -> RegMap Loc -> RegMap Loc
forall a b. (a -> b) -> a -> b
$
                      RegMap Loc
assig
                      -- This is non-deterministic but we do not
                      -- currently support deterministic code-generation.
                      -- See Note [Unique Determinism and code generation]
                let candidates :: [(Unique, Loc)]
candidates = RegMap Loc -> [(Unique, Loc)]
forall elt. UniqFM elt -> [(Unique, elt)]
nonDetUFMToList RegMap Loc
candidates'

                -- the vregs we could kick out that are already in a slot
                let candidates_inBoth :: [(Unique, RealReg, Int)]
candidates_inBoth
                        = [ (Unique
temp, RealReg
reg, Int
mem)
                          | (Unique
temp, InBoth RealReg
reg Int
mem) <- [(Unique, Loc)]
candidates
                          , Platform -> RealReg -> RegClass
targetClassOfRealReg Platform
platform RealReg
reg RegClass -> RegClass -> Bool
forall a. Eq a => a -> a -> Bool
== VirtualReg -> RegClass
classOfVirtualReg VirtualReg
r ]

                -- the vregs we could kick out that are only in a reg
                --      this would require writing the reg to a new slot before using it.
                let candidates_inReg :: [(Unique, RealReg)]
candidates_inReg
                        = [ (Unique
temp, RealReg
reg)
                          | (Unique
temp, InReg RealReg
reg) <- [(Unique, Loc)]
candidates
                          , Platform -> RealReg -> RegClass
targetClassOfRealReg Platform
platform RealReg
reg RegClass -> RegClass -> Bool
forall a. Eq a => a -> a -> Bool
== VirtualReg -> RegClass
classOfVirtualReg VirtualReg
r ]

                let result :: RegM freeRegs ([instr], [RealReg])
result

                        -- we have a temporary that is in both register and mem,
                        -- just free up its register for use.
                        | (Unique
temp, RealReg
my_reg, Int
slot) : [(Unique, RealReg, Int)]
_      <- [(Unique, RealReg, Int)]
candidates_inBoth
                        = do    [instr]
spills' <- VirtualReg
-> SpillLoc -> RealReg -> [instr] -> RegM freeRegs [instr]
forall instr freeRegs.
Instruction instr =>
VirtualReg
-> SpillLoc -> RealReg -> [instr] -> RegM freeRegs [instr]
loadTemp VirtualReg
r SpillLoc
spill_loc RealReg
my_reg [instr]
spills
                                let assig1 :: RegMap Loc
assig1  = RegMap Loc -> Unique -> Loc -> RegMap Loc
forall key elt.
Uniquable key =>
UniqFM elt -> key -> elt -> UniqFM elt
addToUFM RegMap Loc
assig Unique
temp (Int -> Loc
InMem Int
slot)
                                let assig2 :: RegMap Loc
assig2  = RegMap Loc -> VirtualReg -> Loc -> RegMap Loc
forall key elt.
Uniquable key =>
UniqFM elt -> key -> elt -> UniqFM elt
addToUFM RegMap Loc
assig1 VirtualReg
r (Loc -> RegMap Loc) -> Loc -> RegMap Loc
forall a b. (a -> b) -> a -> b
$! SpillLoc -> RealReg -> Loc
newLocation SpillLoc
spill_loc RealReg
my_reg

                                RegMap Loc -> RegM freeRegs ()
forall freeRegs. RegMap Loc -> RegM freeRegs ()
setAssigR RegMap Loc
assig2
                                Bool
-> [VirtualReg]
-> [instr]
-> [RealReg]
-> [VirtualReg]
-> RegM freeRegs ([instr], [RealReg])
forall freeRegs instr.
(FR freeRegs, Outputable instr, Instruction instr) =>
Bool
-> [VirtualReg]
-> [instr]
-> [RealReg]
-> [VirtualReg]
-> RegM freeRegs ([instr], [RealReg])
allocateRegsAndSpill Bool
reading [VirtualReg]
keep [instr]
spills' (RealReg
my_regRealReg -> [RealReg] -> [RealReg]
forall a. a -> [a] -> [a]
:[RealReg]
alloc) [VirtualReg]
rs

                        -- otherwise, we need to spill a temporary that currently
                        -- resides in a register.
                        | (Unique
temp_to_push_out, (RealReg
my_reg :: RealReg)) : [(Unique, RealReg)]
_
                                        <- [(Unique, RealReg)]
candidates_inReg
                        = do
                                (instr
spill_insn, Int
slot) <- Reg -> Unique -> RegM freeRegs (instr, Int)
forall instr freeRegs.
Instruction instr =>
Reg -> Unique -> RegM freeRegs (instr, Int)
spillR (RealReg -> Reg
RegReal RealReg
my_reg) Unique
temp_to_push_out
                                let spill_store :: [instr]
spill_store  = (if Bool
reading then [instr] -> [instr]
forall a. a -> a
id else [instr] -> [instr]
forall a. [a] -> [a]
reverse)
                                                        [ -- COMMENT (fsLit "spill alloc")
                                                           instr
spill_insn ]

                                -- record that this temp was spilled
                                SpillReason -> RegM freeRegs ()
forall freeRegs. SpillReason -> RegM freeRegs ()
recordSpill (Unique -> SpillReason
SpillAlloc Unique
temp_to_push_out)

                                -- update the register assignment
                                let assig1 :: RegMap Loc
assig1  = RegMap Loc -> Unique -> Loc -> RegMap Loc
forall key elt.
Uniquable key =>
UniqFM elt -> key -> elt -> UniqFM elt
addToUFM RegMap Loc
assig Unique
temp_to_push_out   (Int -> Loc
InMem Int
slot)
                                let assig2 :: RegMap Loc
assig2  = RegMap Loc -> VirtualReg -> Loc -> RegMap Loc
forall key elt.
Uniquable key =>
UniqFM elt -> key -> elt -> UniqFM elt
addToUFM RegMap Loc
assig1 VirtualReg
r                 (Loc -> RegMap Loc) -> Loc -> RegMap Loc
forall a b. (a -> b) -> a -> b
$! SpillLoc -> RealReg -> Loc
newLocation SpillLoc
spill_loc RealReg
my_reg
                                RegMap Loc -> RegM freeRegs ()
forall freeRegs. RegMap Loc -> RegM freeRegs ()
setAssigR RegMap Loc
assig2

                                -- if need be, load up a spilled temp into the reg we've just freed up.
                                [instr]
spills' <- VirtualReg
-> SpillLoc -> RealReg -> [instr] -> RegM freeRegs [instr]
forall instr freeRegs.
Instruction instr =>
VirtualReg
-> SpillLoc -> RealReg -> [instr] -> RegM freeRegs [instr]
loadTemp VirtualReg
r SpillLoc
spill_loc RealReg
my_reg [instr]
spills

                                Bool
-> [VirtualReg]
-> [instr]
-> [RealReg]
-> [VirtualReg]
-> RegM freeRegs ([instr], [RealReg])
forall freeRegs instr.
(FR freeRegs, Outputable instr, Instruction instr) =>
Bool
-> [VirtualReg]
-> [instr]
-> [RealReg]
-> [VirtualReg]
-> RegM freeRegs ([instr], [RealReg])
allocateRegsAndSpill Bool
reading [VirtualReg]
keep
                                        ([instr]
spill_store [instr] -> [instr] -> [instr]
forall a. [a] -> [a] -> [a]
++ [instr]
spills')
                                        (RealReg
my_regRealReg -> [RealReg] -> [RealReg]
forall a. a -> [a] -> [a]
:[RealReg]
alloc) [VirtualReg]
rs


                        -- there wasn't anything to spill, so we're screwed.
                        | Bool
otherwise
                        = String -> SDoc -> RegM freeRegs ([instr], [RealReg])
forall a. HasCallStack => String -> SDoc -> a
pprPanic (String
"RegAllocLinear.allocRegsAndSpill: no spill candidates\n")
                        (SDoc -> RegM freeRegs ([instr], [RealReg]))
-> SDoc -> RegM freeRegs ([instr], [RealReg])
forall a b. (a -> b) -> a -> b
$ [SDoc] -> SDoc
vcat
                                [ String -> SDoc
text String
"allocating vreg:  " SDoc -> SDoc -> SDoc
<> String -> SDoc
text (VirtualReg -> String
forall a. Show a => a -> String
show VirtualReg
r)
                                , String -> SDoc
text String
"assignment:       " SDoc -> SDoc -> SDoc
<> RegMap Loc -> SDoc
forall a. Outputable a => a -> SDoc
ppr RegMap Loc
assig
                                , String -> SDoc
text String
"freeRegs:         " SDoc -> SDoc -> SDoc
<> String -> SDoc
text (freeRegs -> String
forall a. Show a => a -> String
show freeRegs
freeRegs)
                                , String -> SDoc
text String
"initFreeRegs:     " SDoc -> SDoc -> SDoc
<> String -> SDoc
text (freeRegs -> String
forall a. Show a => a -> String
show (Platform -> freeRegs
forall freeRegs. FR freeRegs => Platform -> freeRegs
frInitFreeRegs Platform
platform freeRegs -> freeRegs -> freeRegs
forall a. a -> a -> a
`asTypeOf` freeRegs
freeRegs)) ]

                RegM freeRegs ([instr], [RealReg])
result


-- | Calculate a new location after a register has been loaded.
newLocation :: SpillLoc -> RealReg -> Loc
-- if the tmp was read from a slot, then now its in a reg as well
newLocation :: SpillLoc -> RealReg -> Loc
newLocation (ReadMem Int
slot) RealReg
my_reg = RealReg -> Int -> Loc
InBoth RealReg
my_reg Int
slot
-- writes will always result in only the register being available
newLocation SpillLoc
_ RealReg
my_reg = RealReg -> Loc
InReg RealReg
my_reg

-- | Load up a spilled temporary if we need to (read from memory).
loadTemp
        :: (Instruction instr)
        => VirtualReg   -- the temp being loaded
        -> SpillLoc     -- the current location of this temp
        -> RealReg      -- the hreg to load the temp into
        -> [instr]
        -> RegM freeRegs [instr]

loadTemp :: VirtualReg
-> SpillLoc -> RealReg -> [instr] -> RegM freeRegs [instr]
loadTemp VirtualReg
vreg (ReadMem Int
slot) RealReg
hreg [instr]
spills
 = do
        instr
insn <- Reg -> Int -> RegM freeRegs instr
forall instr freeRegs.
Instruction instr =>
Reg -> Int -> RegM freeRegs instr
loadR (RealReg -> Reg
RegReal RealReg
hreg) Int
slot
        SpillReason -> RegM freeRegs ()
forall freeRegs. SpillReason -> RegM freeRegs ()
recordSpill (Unique -> SpillReason
SpillLoad (Unique -> SpillReason) -> Unique -> SpillReason
forall a b. (a -> b) -> a -> b
$ VirtualReg -> Unique
forall a. Uniquable a => a -> Unique
getUnique VirtualReg
vreg)
        [instr] -> RegM freeRegs [instr]
forall (m :: * -> *) a. Monad m => a -> m a
return  ([instr] -> RegM freeRegs [instr])
-> [instr] -> RegM freeRegs [instr]
forall a b. (a -> b) -> a -> b
$  {- COMMENT (fsLit "spill load") : -} instr
insn instr -> [instr] -> [instr]
forall a. a -> [a] -> [a]
: [instr]
spills

loadTemp VirtualReg
_ SpillLoc
_ RealReg
_ [instr]
spills =
   [instr] -> RegM freeRegs [instr]
forall (m :: * -> *) a. Monad m => a -> m a
return [instr]
spills