module ForSyDe.Deep.Backend.VHDL
(writeVHDL,
writeVHDLOps,
writeAndModelsimVHDL,
writeAndModelsimVHDLOps,
writeAndGhdlVHDL,
writeAndGhdlVHDLOps,
VHDLOps(..),
QuartusOps(..),
QuartusAction(..),
checkSynthesisQuartus,
VHDLDebugLevel(..),
VHDLRecursivity(..),
defaultVHDLOps) where
import Control.Monad.State (evalStateT)
import qualified Language.Haskell.TH as TH
import ForSyDe.Deep.System.SysFun
import ForSyDe.Deep.ForSyDeErr
import ForSyDe.Deep.OSharing (readURef)
import ForSyDe.Deep.System.SysDef
import ForSyDe.Deep.Backend.VHDL.Traverse
import ForSyDe.Deep.Backend.VHDL.Modelsim
import ForSyDe.Deep.Backend.VHDL.Ghdl
writeVHDL :: SysDef a -> IO ()
writeVHDL = writeVHDLOps defaultVHDLOps
writeVHDLOps :: VHDLOps -> SysDef a -> IO ()
writeVHDLOps ops sysDef = do
let sinit = initVHDLTravST $ (readURef.unPrimSysDef.unSysDef) sysDef
res <- runErrorT $ evalStateT (setVHDLOps ops >> writeVHDLM) sinit
either printVHDLError return res
writeAndModelsimVHDL :: SysFunToIOSimFun sysF simF =>
Maybe Int
-> SysDef sysF
-> simF
writeAndModelsimVHDL = writeAndModelsimVHDLOps defaultVHDLOps
writeAndModelsimVHDLOps :: SysFunToIOSimFun sysF simF =>
VHDLOps -> Maybe Int -> SysDef sysF -> simF
writeAndModelsimVHDLOps ops mCycles sysDef = fromTHStrSimFun simIO []
where sinit = initVHDLTravST $ (readURef.unPrimSysDef.unSysDef) sysDef
simVHDLM :: [[TH.Exp]] -> VHDLM [[String]]
simVHDLM stimuli = do
setVHDLOps ops{compileModelsim=True}
writeVHDLM
executeTestBenchModelsim mCycles stimuli
simIO :: [[TH.Exp]] -> IO [[String]]
simIO stimuli = do
res <- runErrorT $ evalStateT (simVHDLM stimuli) sinit
either printVHDLError return res
writeAndGhdlVHDL :: SysFunToIOSimFun sysF simF =>
Maybe Int
-> SysDef sysF
-> simF
writeAndGhdlVHDL = writeAndGhdlVHDLOps defaultVHDLOps
writeAndGhdlVHDLOps :: SysFunToIOSimFun sysF simF =>
VHDLOps -> Maybe Int -> SysDef sysF -> simF
writeAndGhdlVHDLOps ops mCycles sysDef = fromTHStrSimFun simIO []
where sinit = initVHDLTravST $ (readURef.unPrimSysDef.unSysDef) sysDef
simVHDLM :: [[TH.Exp]] -> VHDLM [[String]]
simVHDLM stimuli = do
setVHDLOps ops
writeVHDLM
executeTestBenchGhdl mCycles stimuli
simIO :: [[TH.Exp]] -> IO [[String]]
simIO stimuli = do
res <- runErrorT $ evalStateT (simVHDLM stimuli) sinit
either printVHDLError return res