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Given a System Definition whose name is a valid VHDL _basic_ identifier (call it "A") generate A.vhd in current working directory using default compilation options. Imp: the input and output signal names of A must be valid VHDL identifiers (basic or extended) and different to clk and reset which are reserved for the main clock and reset signals

writeVHDL-alternative which allows setting VHDL compilation options.

Generate a function which, given a system definition and some simulation stimuli:

1. Writes a VHDL model of the system
2. Simulates the VHDL model with Modelsim getting the results back to Haskell

VHDLOps-alternative of writeAndModelsimVHDL, note that compileModelSim will implicitly be set to True

Generate a function which, given a system definition and some simulation stimuli:

1. Writes a VHDL model of the system
2. Simulates the VHDL model with Ghdl getting the results back to Haskell

VHDLOps-alternative of writeAndGhdlVHDL

VHDL Compilation options

Options passed to Quartus II by the VHDL Backend. Most of them are optional and Quartus will use a default value.

It contains:

• What action to perform
• Optinally, the minimum acceptable clock frequency (fMax) expressed in MHz
• FPGA family and specific device model (both are independently optional).
• Pin assignments, in the form (VHDL Pin, FPGA Pin). Note that Quartus will automatically split composite VHDL ports

Action to perform by Quartus

Options to check if the model is synthesizable, all options except the action to take are set to default.

Debug level

Recursivity, should the parent systems of system instances be compiled as well?

Default traversing options