CλaSH (pronounced ‘clash’) is a functional hardware description language that borrows both its syntax and semantics from the functional programming language Haskell. The CλaSH compiler transforms these high-level descriptions to low-level synthesizable VHDL, Verilog, or SystemVerilog.

Features of CλaSH:

• Strongly typed (like VHDL), yet with a very high degree of type inference, enabling both safe and fast prototying using consise descriptions (like Verilog).

• Interactive REPL: load your designs in an interpreter and easily test all your component without needing to setup a test bench.

• Higher-order functions, with type inference, result in designs that are fully parametric by default.

• Synchronous sequential circuit design based on streams of values, called Signals, lead to natural descriptions of feedback loops.

• Support for multiple clock domains, with type safe clock domain crossing.

This package provides:

• Verilog Backend

---

[Skip to Readme]

Modules

[Last Documentation]

Downloads

• clash-verilog-0.6.6.tar.gz [browse] (Cabal source package)
• Package description (revised from the package)

Note: This package has metadata revisions in the cabal description newer than included in the tarball. To unpack the package including the revisions, use 'cabal get'.

Maintainer's Corner

Package maintainers

• ChristiaanBaaij

For package maintainers and hackage trustees

• edit package information

Candidates

• No Candidates