clash-lib-0.99.1: CAES Language for Synchronous Hardware - As a Library

Copyright(C) 2015-2016 University of Twente
2017 Myrtle Software Ltd Google Inc.
LicenseBSD2 (see the file LICENSE)
MaintainerChristiaan Baaij <christiaan.baaij@gmail.com>
Safe HaskellNone
LanguageHaskell2010

Clash.Backend

Description

 
Synopsis

Documentation

data Usage Source #

Is a type used for internal or external use

Constructors

Internal

Internal use

External Text

External use, field indicates the library name

class Backend state where Source #

Methods

initBackend :: Int -> HdlSyn -> state Source #

Initial state for state monad

hdlKind :: state -> HDL Source #

What HDL is the backend generating

primDirs :: state -> IO [FilePath] Source #

Location for the primitive definitions

name :: state -> String Source #

Name of backend, used for directory to put output files in. Should be | constant function / ignore argument.

extension :: state -> String Source #

File extension for target langauge

extractTypes :: state -> HashSet HWType Source #

Get the set of types out of state

genHDL :: String -> SrcSpan -> Component -> Mon (State state) ((String, Doc), [(String, Doc)]) Source #

Generate HDL for a Netlist component

mkTyPackage :: String -> [HWType] -> Mon (State state) [(String, Doc)] Source #

Generate a HDL package containing type definitions for the given HWTypes

hdlType :: Usage -> HWType -> Mon (State state) Doc Source #

Convert a Netlist HWType to a target HDL type

hdlTypeErrValue :: HWType -> Mon (State state) Doc Source #

Convert a Netlist HWType to an HDL error value for that type

hdlTypeMark :: HWType -> Mon (State state) Doc Source #

Convert a Netlist HWType to the root of a target HDL type

hdlRecSel :: HWType -> Int -> Mon (State state) Doc Source #

Create a record selector

hdlSig :: Text -> HWType -> Mon (State state) Doc Source #

Create a signal declaration from an identifier (Text) and Netlist HWType

genStmt :: Bool -> State state Doc Source #

Create a generative block statement marker

inst :: Declaration -> Mon (State state) (Maybe Doc) Source #

Turn a Netlist Declaration to a HDL concurrent block

expr :: Bool -> Expr -> Mon (State state) Doc Source #

Turn a Netlist expression into a HDL expression

iwWidth :: State state Int Source #

Bit-width of IntWordInteger

toBV :: HWType -> Text -> Mon (State state) Doc Source #

Convert to a bit-vector

fromBV :: HWType -> Text -> Mon (State state) Doc Source #

Convert from a bit-vector

hdlSyn :: State state HdlSyn Source #

Synthesis tool we're generating HDL for

mkIdentifier :: State state (IdType -> Identifier -> Identifier) Source #

mkIdentifier

extendIdentifier :: State state (IdType -> Identifier -> Identifier -> Identifier) Source #

mkIdentifier

setModName :: ModName -> state -> state Source #

setModName

setSrcSpan :: SrcSpan -> State state () Source #

setSrcSpan

getSrcSpan :: State state SrcSpan Source #

getSrcSpan

blockDecl :: Text -> [Declaration] -> Mon (State state) Doc Source #

Block of declarations

unextend :: State state (Identifier -> Identifier) Source #

unextend/unescape identifier

addInclude :: (String, Doc) -> State state () Source #

addLibraries :: [Text] -> State state () Source #

addImports :: [Text] -> State state () Source #

Instances
Backend VerilogState Source # 
Instance details

Methods

initBackend :: Int -> HdlSyn -> VerilogState Source #

hdlKind :: VerilogState -> HDL Source #

primDirs :: VerilogState -> IO [FilePath] Source #

name :: VerilogState -> String Source #

extension :: VerilogState -> String Source #

extractTypes :: VerilogState -> HashSet HWType Source #

genHDL :: String -> SrcSpan -> Component -> Mon (State VerilogState) ((String, Doc), [(String, Doc)]) Source #

mkTyPackage :: String -> [HWType] -> Mon (State VerilogState) [(String, Doc)] Source #

hdlType :: Usage -> HWType -> Mon (State VerilogState) Doc Source #

hdlTypeErrValue :: HWType -> Mon (State VerilogState) Doc Source #

hdlTypeMark :: HWType -> Mon (State VerilogState) Doc Source #

hdlRecSel :: HWType -> Int -> Mon (State VerilogState) Doc Source #

hdlSig :: Text -> HWType -> Mon (State VerilogState) Doc Source #

genStmt :: Bool -> State VerilogState Doc Source #

inst :: Declaration -> Mon (State VerilogState) (Maybe Doc) Source #

expr :: Bool -> Expr -> Mon (State VerilogState) Doc Source #

iwWidth :: State VerilogState Int Source #

toBV :: HWType -> Text -> Mon (State VerilogState) Doc Source #

fromBV :: HWType -> Text -> Mon (State VerilogState) Doc Source #

hdlSyn :: State VerilogState HdlSyn Source #

mkIdentifier :: State VerilogState (IdType -> Identifier -> Identifier) Source #

extendIdentifier :: State VerilogState (IdType -> Identifier -> Identifier -> Identifier) Source #

setModName :: ModName -> VerilogState -> VerilogState Source #

setSrcSpan :: SrcSpan -> State VerilogState () Source #

getSrcSpan :: State VerilogState SrcSpan Source #

blockDecl :: Text -> [Declaration] -> Mon (State VerilogState) Doc Source #

unextend :: State VerilogState (Identifier -> Identifier) Source #

addInclude :: (String, Doc) -> State VerilogState () Source #

addLibraries :: [Text] -> State VerilogState () Source #

addImports :: [Text] -> State VerilogState () Source #

Backend VHDLState Source # 
Instance details

Methods

initBackend :: Int -> HdlSyn -> VHDLState Source #

hdlKind :: VHDLState -> HDL Source #

primDirs :: VHDLState -> IO [FilePath] Source #

name :: VHDLState -> String Source #

extension :: VHDLState -> String Source #

extractTypes :: VHDLState -> HashSet HWType Source #

genHDL :: String -> SrcSpan -> Component -> Mon (State VHDLState) ((String, Doc), [(String, Doc)]) Source #

mkTyPackage :: String -> [HWType] -> Mon (State VHDLState) [(String, Doc)] Source #

hdlType :: Usage -> HWType -> Mon (State VHDLState) Doc Source #

hdlTypeErrValue :: HWType -> Mon (State VHDLState) Doc Source #

hdlTypeMark :: HWType -> Mon (State VHDLState) Doc Source #

hdlRecSel :: HWType -> Int -> Mon (State VHDLState) Doc Source #

hdlSig :: Text -> HWType -> Mon (State VHDLState) Doc Source #

genStmt :: Bool -> State VHDLState Doc Source #

inst :: Declaration -> Mon (State VHDLState) (Maybe Doc) Source #

expr :: Bool -> Expr -> Mon (State VHDLState) Doc Source #

iwWidth :: State VHDLState Int Source #

toBV :: HWType -> Text -> Mon (State VHDLState) Doc Source #

fromBV :: HWType -> Text -> Mon (State VHDLState) Doc Source #

hdlSyn :: State VHDLState HdlSyn Source #

mkIdentifier :: State VHDLState (IdType -> Identifier -> Identifier) Source #

extendIdentifier :: State VHDLState (IdType -> Identifier -> Identifier -> Identifier) Source #

setModName :: ModName -> VHDLState -> VHDLState Source #

setSrcSpan :: SrcSpan -> State VHDLState () Source #

getSrcSpan :: State VHDLState SrcSpan Source #

blockDecl :: Text -> [Declaration] -> Mon (State VHDLState) Doc Source #

unextend :: State VHDLState (Identifier -> Identifier) Source #

addInclude :: (String, Doc) -> State VHDLState () Source #

addLibraries :: [Text] -> State VHDLState () Source #

addImports :: [Text] -> State VHDLState () Source #

Backend SystemVerilogState Source # 
Instance details

Methods

initBackend :: Int -> HdlSyn -> SystemVerilogState Source #

hdlKind :: SystemVerilogState -> HDL Source #

primDirs :: SystemVerilogState -> IO [FilePath] Source #

name :: SystemVerilogState -> String Source #

extension :: SystemVerilogState -> String Source #

extractTypes :: SystemVerilogState -> HashSet HWType Source #

genHDL :: String -> SrcSpan -> Component -> Mon (State SystemVerilogState) ((String, Doc), [(String, Doc)]) Source #

mkTyPackage :: String -> [HWType] -> Mon (State SystemVerilogState) [(String, Doc)] Source #

hdlType :: Usage -> HWType -> Mon (State SystemVerilogState) Doc Source #

hdlTypeErrValue :: HWType -> Mon (State SystemVerilogState) Doc Source #

hdlTypeMark :: HWType -> Mon (State SystemVerilogState) Doc Source #

hdlRecSel :: HWType -> Int -> Mon (State SystemVerilogState) Doc Source #

hdlSig :: Text -> HWType -> Mon (State SystemVerilogState) Doc Source #

genStmt :: Bool -> State SystemVerilogState Doc Source #

inst :: Declaration -> Mon (State SystemVerilogState) (Maybe Doc) Source #

expr :: Bool -> Expr -> Mon (State SystemVerilogState) Doc Source #

iwWidth :: State SystemVerilogState Int Source #

toBV :: HWType -> Text -> Mon (State SystemVerilogState) Doc Source #

fromBV :: HWType -> Text -> Mon (State SystemVerilogState) Doc Source #

hdlSyn :: State SystemVerilogState HdlSyn Source #

mkIdentifier :: State SystemVerilogState (IdType -> Identifier -> Identifier) Source #

extendIdentifier :: State SystemVerilogState (IdType -> Identifier -> Identifier -> Identifier) Source #

setModName :: ModName -> SystemVerilogState -> SystemVerilogState Source #

setSrcSpan :: SrcSpan -> State SystemVerilogState () Source #

getSrcSpan :: State SystemVerilogState SrcSpan Source #

blockDecl :: Text -> [Declaration] -> Mon (State SystemVerilogState) Doc Source #

unextend :: State SystemVerilogState (Identifier -> Identifier) Source #

addInclude :: (String, Doc) -> State SystemVerilogState () Source #

addLibraries :: [Text] -> State SystemVerilogState () Source #

addImports :: [Text] -> State SystemVerilogState () Source #

nestM :: Modifier -> Modifier -> Maybe Modifier Source #

Try to merge nested modifiers into a single modifier, needed by the VHDL and SystemVerilog backend.

escapeTemplate :: Identifier -> Identifier Source #

Replace a normal HDL template placeholder with an unescaped/unextended template placeholder.

Needed when the the place-holder is filled with an escaped/extended identifier inside an escaped/extended identifier and we want to strip the escape /extension markers. Otherwise we end up with illegal identifiers.