Safe Haskell | None |
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Xilinx Lava is a library for FPGA circuit design with a focus on circuit layout.
- (->-) :: (a -> Out b) -> (b -> Out c) -> a -> Out c
- (>->) :: (a -> Out b) -> (b -> Out c) -> a -> Out c
- (>=>) :: (a -> Out b) -> (b -> Out c) -> a -> Out c
- (>|>) :: (a -> Out b) -> (b -> Out c) -> a -> Out c
- condShift :: (Int -> Bool, Int -> Int) -> (Int -> Bool, Int -> Int) -> Out ()
- hRepN :: Int -> (a -> Out a) -> a -> Out a
- par2 :: (a -> Out c) -> (b -> Out d) -> (a, b) -> Out (c, d)
- maP :: (a -> Out b) -> [a] -> Out [b]
- mapPair :: ((a, a) -> Out a) -> [a] -> Out [a]
- hpar2 :: (a -> Out c) -> (b -> Out d) -> (a, b) -> Out (c, d)
- hmaP :: (a -> Out b) -> [a] -> Out [b]
- par2Overlay :: (a -> Out c) -> (b -> Out d) -> (a, b) -> Out (c, d)
- par3Overlay :: (a -> Out ao) -> (b -> Out bo) -> (c -> Out co) -> (a, b, c) -> Out (ao, bo, co)
- hpar :: [a -> Out b] -> [a] -> Out [b]
- hparN :: Int -> (a -> Out b) -> [a] -> Out [b]
- fork2 :: a -> Out (a, a)
- listToPair :: [a] -> Out (a, a)
- pairToList :: (a, a) -> Out [a]
- ziP :: ([a], [b]) -> Out [(a, b)]
- unziP :: [(a, b)] -> Out ([a], [b])
- zipList :: [[a]] -> Out [[a]]
- unzipList :: [[a]] -> Out [[a]]
- fstListPair :: [a] -> a
- sndListPair :: [a] -> a
- pair :: [a] -> Out [[a]]
- unpair :: [[a]] -> Out [a]
- halveListToPair :: [a] -> ([a], [a])
- halve :: [a] -> Out ([a], [a])
- unhalve :: ([a], [a]) -> Out [a]
- halveList :: [a] -> Out [[a]]
- unhalveList :: [[a]] -> Out [a]
- chop :: Int -> [a] -> Out [[a]]
- chopPair :: [a] -> Out [(a, a)]
- concaT :: [[a]] -> Out [a]
- fstList :: ([a] -> Out [a]) -> [a] -> Out [a]
- sndList :: ([a] -> Out [a]) -> [a] -> Out [a]
- fsT :: (a -> Out b) -> (a, c) -> Out (b, c)
- snD :: (b -> Out c) -> (a, b) -> Out (a, c)
- projectFst :: (a, b) -> Out a
- projectSnd :: (a, b) -> Out b
- reversE :: [a] -> Out [a]
- inputPort :: String -> NetType -> Out Bit
- inputBitVec :: String -> NetType -> Out [Bit]
- inputArrayOfArray :: String -> NetType -> Out [[Bit]]
- inputLocalArrayOfArray :: String -> NetType -> Out [[Bit]]
- freshBitVec :: Int -> Dir -> Int -> Out [Bit]
- outputArrayOfArray :: String -> NetType -> [[Bit]] -> Out ()
- outputLocalArrayOfArray :: String -> NetType -> [[Bit]] -> Out ()
- inputBitVecLocal :: String -> NetType -> Out [Bit]
- outputPort :: String -> NetType -> Bit -> Out ()
- outputBitVec :: String -> NetType -> [Bit] -> Out ()
- outputBitVecLocal :: String -> NetType -> [Bit] -> Out ()
- declareType :: String -> NetType -> Out NetType
- data Dir
- data NetType
- data Netlist
- type Out a = State Netlist a
- type Bit = Int
- data XilinxArchitecture
- setOrigin :: (Int, Int) -> Out ()
- col :: ((a, b) -> Out (c, a)) -> (a, [b]) -> Out ([c], a)
- computeNetlist :: String -> XilinxArchitecture -> Out () -> Netlist
- preLayoutNetlist :: String -> XilinxArchitecture -> Out () -> Netlist
- putXilinxVHDL :: Netlist -> IO ()
- vhdlPackage :: Handle -> String -> [PortDeclaration] -> [(String, NetType)] -> IO ()
- overlayTile :: Out a -> Out a
- middle :: (a -> Out c) -> ((c, d) -> Out e) -> (b -> Out d) -> (a, b) -> Out e
- primitiveGate :: String -> [(String, Bit)] -> [String] -> Maybe (Int, Int) -> Out [Bit]
- instantiate :: String -> Out () -> [(String, Bit)] -> [String] -> Out [Bit]
- putXilinxEDIF :: Netlist -> IO ()
- putDriver :: Handle -> [(String, NetType)] -> Array Int DrivenPorts -> [PortDeclaration] -> Int -> IO ()
- preamble :: Handle -> Netlist -> IO ()
- postamble :: Handle -> Netlist -> IO ()
- declareComponents :: Handle -> [String] -> [Instance] -> IO ()
- declareComponent :: Handle -> Instance -> IO ()
- declareCell :: Handle -> String -> [String] -> [String] -> IO ()
- mainPreamble :: Handle -> Netlist -> IO ()
- putEDIFPort :: Handle -> [(String, NetType)] -> PortDeclaration -> IO ()
- putArrayOfArrayPort :: Handle -> String -> String -> Int -> Int -> IO ()
- putEDIFInstance :: Handle -> Netlist -> Instance -> IO ()
- putLUTInstance :: Handle -> Netlist -> Instance -> [Int] -> IO ()
- putPrimitiveInstance :: Handle -> Netlist -> Instance -> IO ()
- edifLUTInit :: [Int] -> String
- binaryListToInt :: [Int] -> Int
- powersOfTwo :: [Int]
- declareBUF :: Handle -> IO ()
- declareBUFInstances :: Handle -> [PortDeclaration] -> IO ()
- declareBUFInstance :: Handle -> PortDeclaration -> IO ()
- putPortWires :: Handle -> [(String, NetType)] -> Int -> [PortDeclaration] -> IO ()
- putPortWire :: Handle -> [(String, NetType)] -> Int -> PortDeclaration -> IO ()
- findConnection :: Int -> [Int] -> [Int] -> [Int]
- findConnection2D :: Int -> [[Int]] -> [Int] -> [Int] -> [(Int, Int)]
- putVHDLPackage :: Handle -> Netlist -> IO ()
- lut1gate :: (Bool -> Bool) -> String -> Bit -> Out Bit
- lut2gate :: (Bool -> Bool -> Bool) -> String -> (Bit, Bit) -> Out Bit
- lut2gate_l :: (Bool -> Bool -> Bool) -> String -> (Bit, Bit) -> Out Bit
- lut3gate :: (Bool -> Bool -> Bool -> Bool) -> String -> (Bit, Bit, Bit) -> Out Bit
- lut4gate :: (Bool -> Bool -> Bool -> Bool -> Bool) -> String -> (Bit, Bit, Bit, Bit) -> Out Bit
- lut5gate :: (Bool -> Bool -> Bool -> Bool -> Bool -> Bool) -> String -> (Bit, Bit, Bit, Bit, Bit) -> Out Bit
- lut6gate :: (Bool -> Bool -> Bool -> Bool -> Bool -> Bool -> Bool) -> String -> (Bit, Bit, Bit, Bit, Bit, Bit) -> Out Bit
- lavaVersion :: (Int, Int, Int, Int)
- one :: Bit
- zero :: Bit
Lava Combinators
Serial composition combinators
(>->) :: (a -> Out b) -> (b -> Out c) -> a -> Out cSource
Serial composition with horizontal left to right layout
(>=>) :: (a -> Out b) -> (b -> Out c) -> a -> Out cSource
Serial composition with mid-horizontal left to right layout
Conditional shift for obstacle avoidance
Parallel composition combinators
par2 :: (a -> Out c) -> (b -> Out d) -> (a, b) -> Out (c, d)Source
Vertical parallel composition of two circuits
mapPair :: ((a, a) -> Out a) -> [a] -> Out [a]Source
mapPair
maps a circuit over adajcent pairs of elements in a list
hpar2 :: (a -> Out c) -> (b -> Out d) -> (a, b) -> Out (c, d)Source
Horizontal parallel composition of two circuits
par2Overlay :: (a -> Out c) -> (b -> Out d) -> (a, b) -> Out (c, d)Source
Parallel composition of two circuit which have overlaid layout
par3Overlay :: (a -> Out ao) -> (b -> Out bo) -> (c -> Out co) -> (a, b, c) -> Out (ao, bo, co)Source
Parallel composition of three circuit which have overlaid layout
hparN :: Int -> (a -> Out b) -> [a] -> Out [b]Source
Horizontal repeated parallel composition of a circuit
Wiring combinators
listToPair :: [a] -> Out (a, a)Source
Converts a two element list into a pair
pairToList :: (a, a) -> Out [a]Source
Converts a par into a list containing two elements
zipList :: [[a]] -> Out [[a]]Source
Takes a list containing two elements and returns a list of lists where each element is a two element list
fstListPair :: [a] -> aSource
sndListPair :: [a] -> aSource
halveListToPair :: [a] -> ([a], [a])Source
halveListToPair
will take a list and return a pair containing the
two halves.
halve :: [a] -> Out ([a], [a])Source
Tales a list and returns a pair containing the two halves of the list
unhalveList :: [[a]] -> Out [a]Source
Undoes halveList
projectFst :: (a, b) -> Out aSource
projectSnd :: (a, b) -> Out bSource
Circuit input/output ports
inputBitVec :: String -> NetType -> Out [Bit]Source
inputBitVec
creates a bit-vector input port
inputArrayOfArray :: String -> NetType -> Out [[Bit]]Source
inputArrayOfArray
creates an input array of arrays.
inputLocalArrayOfArray :: String -> NetType -> Out [[Bit]]Source
inputLocalArrayOfArray
creates an input array of arrays.
inputBitVecLocal :: String -> NetType -> Out [Bit]Source
inputBitVecLocal
creates a local bit-vector input port
outputPort :: String -> NetType -> Bit -> Out ()Source
outputPort
creates a single bit output port
outputBitVec :: String -> NetType -> [Bit] -> Out ()Source
outputBitVec
creates a bit-vector output port
outputBitVecLocal :: String -> NetType -> [Bit] -> Out ()Source
outputBitVecKept
creates a bit-vector local signal with a
KEEP attribute set
data XilinxArchitecture Source
:: ((a, b) -> Out (c, a)) | type of element circuit r |
-> (a, [b]) | input to the col |
-> Out ([c], a) | output of the col |
Place four sided tile comoponents in a colum
Generating a Lava netlist
computeNetlist :: String -> XilinxArchitecture -> Out () -> NetlistSource
preLayoutNetlist :: String -> XilinxArchitecture -> Out () -> NetlistSource
putXilinxVHDL :: Netlist -> IO ()Source
vhdlPackage :: Handle -> String -> [PortDeclaration] -> [(String, NetType)] -> IO ()Source
overlayTile :: Out a -> Out aSource
overlayTile takes a circuit instantiation block and overlays all the the instantions.
middle :: (a -> Out c) -> ((c, d) -> Out e) -> (b -> Out d) -> (a, b) -> Out eSource
Place components in a horizontal middle arrangement
Adding new primitive gates to the Lava system
:: String | The name of the component |
-> [(String, Bit)] | name of input ports with argument nets |
-> [String] | name of output ports |
-> Maybe (Int, Int) | optional size information for layout |
-> Out [Bit] | a list of output nets from this component |
primitiveGate
adds a primitive gate
putXilinxEDIF :: Netlist -> IO ()Source
:: Handle | The file to write to |
-> [(String, NetType)] | Type definitions |
-> Array Int DrivenPorts | An array of driven nets |
-> [PortDeclaration] | Port declarations |
-> Int | The net driver t |
-> IO () |
putDriver
writes out the EDIF net driven by source net(i)
declareComponent :: Handle -> Instance -> IO ()Source
mainPreamble :: Handle -> Netlist -> IO ()Source
putEDIFPort :: Handle -> [(String, NetType)] -> PortDeclaration -> IO ()Source
edifLUTInit :: [Int] -> StringSource
binaryListToInt :: [Int] -> IntSource
powersOfTwo :: [Int]Source
declareBUF :: Handle -> IO ()Source
declareBUFInstances :: Handle -> [PortDeclaration] -> IO ()Source
declareBUFInstance :: Handle -> PortDeclaration -> IO ()Source
putPortWires :: Handle -> [(String, NetType)] -> Int -> [PortDeclaration] -> IO ()Source
putPortWire :: Handle -> [(String, NetType)] -> Int -> PortDeclaration -> IO ()Source
findConnection :: Int -> [Int] -> [Int] -> [Int]Source
findConnection
takes a net number and a list of connectiosn
and returns the port indices which are connected to this Lava net.
findConnection2D :: Int -> [[Int]] -> [Int] -> [Int] -> [(Int, Int)]Source
findConnection2D
takes a net number and a list of connectiosn
and returns the 2D port indices which are connected to this Lava net.
putVHDLPackage :: Handle -> Netlist -> IO ()Source
Functions for defining new LUT-based gates
lut1gate :: (Bool -> Bool) -> String -> Bit -> Out BitSource
Implements a user-defined 1 input combinational gate
lut2gate :: (Bool -> Bool -> Bool) -> String -> (Bit, Bit) -> Out BitSource
Implements a user defined two input combinational gate
lut2gate_l :: (Bool -> Bool -> Bool) -> String -> (Bit, Bit) -> Out BitSource
Implements a local user defined two input combinational gate
lut3gate :: (Bool -> Bool -> Bool -> Bool) -> String -> (Bit, Bit, Bit) -> Out BitSource
Implements a user defined three input combinational gate
lut4gate :: (Bool -> Bool -> Bool -> Bool -> Bool) -> String -> (Bit, Bit, Bit, Bit) -> Out BitSource
Implements a user defined four input combinational gate
lut5gate :: (Bool -> Bool -> Bool -> Bool -> Bool -> Bool) -> String -> (Bit, Bit, Bit, Bit, Bit) -> Out BitSource
Implements a user defined five input combinational gate
lut6gate :: (Bool -> Bool -> Bool -> Bool -> Bool -> Bool -> Bool) -> String -> (Bit, Bit, Bit, Bit, Bit, Bit) -> Out BitSource
Implements a user defined six input combinational gate