module Verismith.Verilog.Internal
( regDecl
, wireDecl
, emptyMod
, setModName
, addModPort
, addModDecl
, testBench
, addTestBench
, defaultPort
, portToExpr
, modName
, yPort
, wire
, reg
)
where
import Control.Lens
import Data.Text (Text)
import Verismith.Verilog.AST
regDecl :: Identifier -> ModItem
regDecl i = Decl Nothing (Port Reg False (Range 1 0) i) Nothing
wireDecl :: Identifier -> ModItem
wireDecl i = Decl Nothing (Port Wire False (Range 1 0) i) Nothing
emptyMod :: ModDecl
emptyMod = ModDecl "" [] [] [] []
setModName :: Text -> ModDecl -> ModDecl
setModName str = modId .~ Identifier str
addModPort :: Port -> ModDecl -> ModDecl
addModPort port = modInPorts %~ (:) port
addModDecl :: ModDecl -> Verilog -> Verilog
addModDecl desc = _Wrapped %~ (:) desc
testBench :: ModDecl
testBench = ModDecl
"main"
[]
[]
[ regDecl "a"
, regDecl "b"
, wireDecl "c"
, ModInst "and"
"and_gate"
[ModConn $ Id "c", ModConn $ Id "a", ModConn $ Id "b"]
, Initial $ SeqBlock
[ BlockAssign . Assign (RegId "a") Nothing $ Number 1
, BlockAssign . Assign (RegId "b") Nothing $ Number 1
]
]
[]
addTestBench :: Verilog -> Verilog
addTestBench = addModDecl testBench
defaultPort :: Identifier -> Port
defaultPort = Port Wire False (Range 1 0)
portToExpr :: Port -> Expr
portToExpr (Port _ _ _ i) = Id i
modName :: ModDecl -> Text
modName = getIdentifier . view modId
yPort :: Identifier -> Port
yPort = Port Wire False (Range 90 0)
wire :: Range -> Identifier -> Port
wire = Port Wire False
reg :: Range -> Identifier -> Port
reg = Port Reg False