Copyright | (c) 2019 Yann Herklotz Grave |
---|---|
License | GPL-3 |
Maintainer | yann [at] yannherklotz [dot] com |
Stability | experimental |
Portability | POSIX |
Safe Haskell | None |
Language | Haskell2010 |
Verilog implementation with random generation and mutations.
Synopsis
- data SourceInfo = SourceInfo {}
- newtype Verilog = Verilog {
- getVerilog :: [ModDecl]
- parseVerilog :: Text -> Text -> Either Text Verilog
- newtype GenVerilog a = GenVerilog {
- unGenVerilog :: a
- genSource :: Source a => a -> Text
- newtype Identifier = Identifier {}
- newtype Delay = Delay {}
- data Event
- = EId !Identifier
- | EExpr !Expr
- | EAll
- | EPosEdge !Identifier
- | ENegEdge !Identifier
- | EOr !Event !Event
- | EComb !Event !Event
- data BinaryOperator
- data UnaryOperator
- data Task = Task {
- _taskName :: !Identifier
- _taskExpr :: [Expr]
- taskName :: Lens' Task Identifier
- taskExpr :: Lens' Task [Expr]
- data LVal
- = RegId {
- _regId :: !Identifier
- | RegExpr {
- _regExprId :: !Identifier
- _regExpr :: !Expr
- | RegSize {
- _regSizeId :: !Identifier
- _regSizeRange :: !Range
- | RegConcat { }
- = RegId {
- regId :: Traversal' LVal Identifier
- regExprId :: Traversal' LVal Identifier
- regExpr :: Traversal' LVal Expr
- regSizeId :: Traversal' LVal Identifier
- regSizeRange :: Traversal' LVal Range
- regConc :: Traversal' LVal [Expr]
- data PortDir
- data PortType
- data Port = Port {
- _portType :: !PortType
- _portSigned :: !Bool
- _portSize :: !Range
- _portName :: !Identifier
- portType :: Lens' Port PortType
- portSigned :: Lens' Port Bool
- portSize :: Lens' Port Range
- portName :: Lens' Port Identifier
- data Expr
- = Number !BitVec
- | Id !Identifier
- | VecSelect !Identifier !Expr
- | RangeSelect !Identifier !Range
- | Concat !(NonEmpty Expr)
- | UnOp !UnaryOperator !Expr
- | BinOp !Expr !BinaryOperator !Expr
- | Cond !Expr !Expr !Expr
- | Appl !Identifier !Expr
- | Str !Text
- data ConstExpr
- = ConstNum { }
- | ParamId { }
- | ConstConcat {
- _constConcat :: !(NonEmpty ConstExpr)
- | ConstUnOp { }
- | ConstBinOp { }
- | ConstCond {
- _constCond :: !ConstExpr
- _constTrue :: !ConstExpr
- _constFalse :: !ConstExpr
- | ConstStr { }
- constToExpr :: ConstExpr -> Expr
- exprToConst :: Expr -> ConstExpr
- constNum :: Traversal' ConstExpr BitVec
- data Assign = Assign {
- _assignReg :: !LVal
- _assignDelay :: !(Maybe Delay)
- _assignExpr :: !Expr
- assignReg :: Lens' Assign LVal
- assignDelay :: Lens' Assign (Maybe Delay)
- assignExpr :: Lens' Assign Expr
- data ContAssign = ContAssign {}
- contAssignNetLVal :: Lens' ContAssign Identifier
- contAssignExpr :: Lens' ContAssign Expr
- data Statement
- = TimeCtrl {
- _statDelay :: !Delay
- _statDStat :: Maybe Statement
- | EventCtrl {
- _statEvent :: !Event
- _statEStat :: Maybe Statement
- | SeqBlock {
- _statements :: [Statement]
- | BlockAssign { }
- | NonBlockAssign { }
- | TaskEnable {
- _stmntTask :: !Task
- | SysTaskEnable {
- _stmntSysTask :: !Task
- | CondStmnt { }
- | ForLoop { }
- = TimeCtrl {
- statDelay :: Traversal' Statement Delay
- statDStat :: Traversal' Statement (Maybe Statement)
- statEvent :: Traversal' Statement Event
- statEStat :: Traversal' Statement (Maybe Statement)
- statements :: Traversal' Statement [Statement]
- stmntBA :: Traversal' Statement Assign
- stmntNBA :: Traversal' Statement Assign
- stmntTask :: Traversal' Statement Task
- stmntSysTask :: Traversal' Statement Task
- stmntCondExpr :: Traversal' Statement Expr
- stmntCondTrue :: Traversal' Statement (Maybe Statement)
- stmntCondFalse :: Traversal' Statement (Maybe Statement)
- data ModDecl = ModDecl {
- _modId :: !Identifier
- _modOutPorts :: ![Port]
- _modInPorts :: ![Port]
- _modItems :: ![ModItem]
- _modParams :: ![Parameter]
- modId :: Lens' ModDecl Identifier
- modOutPorts :: Lens' ModDecl [Port]
- modInPorts :: Lens' ModDecl [Port]
- modItems :: Lens' ModDecl [ModItem]
- data ModItem
- = ModCA { }
- | ModInst {
- _modInstId :: !Identifier
- _modInstName :: !Identifier
- _modInstConns :: [ModConn]
- | Initial !Statement
- | Always !Statement
- | Decl { }
- | ParamDecl { }
- | LocalParamDecl { }
- modContAssign :: Traversal' ModItem ContAssign
- modInstId :: Traversal' ModItem Identifier
- modInstName :: Traversal' ModItem Identifier
- modInstConns :: Traversal' ModItem [ModConn]
- traverseModItem :: Applicative f => (Expr -> f Expr) -> ModItem -> f ModItem
- declDir :: Traversal' ModItem (Maybe PortDir)
- declPort :: Traversal' ModItem Port
- data ModConn
- = ModConn { }
- | ModConnNamed {
- _modConnName :: !Identifier
- _modExpr :: !Expr
- modConnName :: Traversal' ModConn Identifier
- modExpr :: Lens' ModConn Expr
- getModule :: Traversal' Verilog ModDecl
- getSourceId :: Traversal' Verilog Text
- verilog :: QuasiQuoter
Documentation
data SourceInfo Source #
Instances
The complete sourcetext for the Verilog module.
Verilog | |
|
Instances
Eq Verilog Source # | |
Data Verilog Source # | |
Defined in Verismith.Verilog.AST gfoldl :: (forall d b. Data d => c (d -> b) -> d -> c b) -> (forall g. g -> c g) -> Verilog -> c Verilog # gunfold :: (forall b r. Data b => c (b -> r) -> c r) -> (forall r. r -> c r) -> Constr -> c Verilog # toConstr :: Verilog -> Constr # dataTypeOf :: Verilog -> DataType # dataCast1 :: Typeable t => (forall d. Data d => c (t d)) -> Maybe (c Verilog) # dataCast2 :: Typeable t => (forall d e. (Data d, Data e) => c (t d e)) -> Maybe (c Verilog) # gmapT :: (forall b. Data b => b -> b) -> Verilog -> Verilog # gmapQl :: (r -> r' -> r) -> r -> (forall d. Data d => d -> r') -> Verilog -> r # gmapQr :: (r' -> r -> r) -> r -> (forall d. Data d => d -> r') -> Verilog -> r # gmapQ :: (forall d. Data d => d -> u) -> Verilog -> [u] # gmapQi :: Int -> (forall d. Data d => d -> u) -> Verilog -> u # gmapM :: Monad m => (forall d. Data d => d -> m d) -> Verilog -> m Verilog # gmapMp :: MonadPlus m => (forall d. Data d => d -> m d) -> Verilog -> m Verilog # gmapMo :: MonadPlus m => (forall d. Data d => d -> m d) -> Verilog -> m Verilog # | |
Ord Verilog Source # | |
Show Verilog Source # | |
Generic Verilog Source # | |
Semigroup Verilog Source # | |
Monoid Verilog Source # | |
NFData Verilog Source # | |
Defined in Verismith.Verilog.AST | |
Wrapped Verilog Source # | |
Source Verilog Source # | |
Mutate Verilog Source # | |
Verilog ~ t => Rewrapped Verilog t Source # | |
Defined in Verismith.Verilog.AST | |
type Rep Verilog Source # | |
Defined in Verismith.Verilog.AST | |
type Unwrapped Verilog Source # | |
Defined in Verismith.Verilog.AST |
:: Text | Name of parsed object. |
-> Text | Content to be parsed. |
-> Either Text Verilog | Returns |
Parse a String
containing verilog code. The parser currently only supports
the subset of Verilog that is being generated randomly.
newtype GenVerilog a Source #
GenVerilog | |
|
Instances
Eq a => Eq (GenVerilog a) Source # | |
Defined in Verismith.Verilog.CodeGen (==) :: GenVerilog a -> GenVerilog a -> Bool # (/=) :: GenVerilog a -> GenVerilog a -> Bool # | |
Data a => Data (GenVerilog a) Source # | |
Defined in Verismith.Verilog.CodeGen gfoldl :: (forall d b. Data d => c (d -> b) -> d -> c b) -> (forall g. g -> c g) -> GenVerilog a -> c (GenVerilog a) # gunfold :: (forall b r. Data b => c (b -> r) -> c r) -> (forall r. r -> c r) -> Constr -> c (GenVerilog a) # toConstr :: GenVerilog a -> Constr # dataTypeOf :: GenVerilog a -> DataType # dataCast1 :: Typeable t => (forall d. Data d => c (t d)) -> Maybe (c (GenVerilog a)) # dataCast2 :: Typeable t => (forall d e. (Data d, Data e) => c (t d e)) -> Maybe (c (GenVerilog a)) # gmapT :: (forall b. Data b => b -> b) -> GenVerilog a -> GenVerilog a # gmapQl :: (r -> r' -> r) -> r -> (forall d. Data d => d -> r') -> GenVerilog a -> r # gmapQr :: (r' -> r -> r) -> r -> (forall d. Data d => d -> r') -> GenVerilog a -> r # gmapQ :: (forall d. Data d => d -> u) -> GenVerilog a -> [u] # gmapQi :: Int -> (forall d. Data d => d -> u) -> GenVerilog a -> u # gmapM :: Monad m => (forall d. Data d => d -> m d) -> GenVerilog a -> m (GenVerilog a) # gmapMp :: MonadPlus m => (forall d. Data d => d -> m d) -> GenVerilog a -> m (GenVerilog a) # gmapMo :: MonadPlus m => (forall d. Data d => d -> m d) -> GenVerilog a -> m (GenVerilog a) # | |
Ord a => Ord (GenVerilog a) Source # | |
Defined in Verismith.Verilog.CodeGen compare :: GenVerilog a -> GenVerilog a -> Ordering # (<) :: GenVerilog a -> GenVerilog a -> Bool # (<=) :: GenVerilog a -> GenVerilog a -> Bool # (>) :: GenVerilog a -> GenVerilog a -> Bool # (>=) :: GenVerilog a -> GenVerilog a -> Bool # max :: GenVerilog a -> GenVerilog a -> GenVerilog a # min :: GenVerilog a -> GenVerilog a -> GenVerilog a # | |
Source a => Show (GenVerilog a) Source # | |
Defined in Verismith.Verilog.CodeGen showsPrec :: Int -> GenVerilog a -> ShowS # show :: GenVerilog a -> String # showList :: [GenVerilog a] -> ShowS # | |
Mutate a => Mutate (GenVerilog a) Source # | |
Defined in Verismith.Verilog.Mutate mutExpr :: (Expr -> Expr) -> GenVerilog a -> GenVerilog a Source # |
Primitives
Identifier
newtype Identifier Source #
Identifier in Verilog. This is just a string of characters that can either be lowercase and uppercase for now. This might change in the future though, as Verilog supports many more characters in Identifiers.
Instances
Control
Verilog syntax for adding a delay, which is represented as #num
.
Instances
Eq Delay Source # | |
Data Delay Source # | |
Defined in Verismith.Verilog.AST gfoldl :: (forall d b. Data d => c (d -> b) -> d -> c b) -> (forall g. g -> c g) -> Delay -> c Delay # gunfold :: (forall b r. Data b => c (b -> r) -> c r) -> (forall r. r -> c r) -> Constr -> c Delay # dataTypeOf :: Delay -> DataType # dataCast1 :: Typeable t => (forall d. Data d => c (t d)) -> Maybe (c Delay) # dataCast2 :: Typeable t => (forall d e. (Data d, Data e) => c (t d e)) -> Maybe (c Delay) # gmapT :: (forall b. Data b => b -> b) -> Delay -> Delay # gmapQl :: (r -> r' -> r) -> r -> (forall d. Data d => d -> r') -> Delay -> r # gmapQr :: (r' -> r -> r) -> r -> (forall d. Data d => d -> r') -> Delay -> r # gmapQ :: (forall d. Data d => d -> u) -> Delay -> [u] # gmapQi :: Int -> (forall d. Data d => d -> u) -> Delay -> u # gmapM :: Monad m => (forall d. Data d => d -> m d) -> Delay -> m Delay # gmapMp :: MonadPlus m => (forall d. Data d => d -> m d) -> Delay -> m Delay # gmapMo :: MonadPlus m => (forall d. Data d => d -> m d) -> Delay -> m Delay # | |
Num Delay Source # | |
Ord Delay Source # | |
Show Delay Source # | |
Generic Delay Source # | |
NFData Delay Source # | |
Defined in Verismith.Verilog.AST | |
Wrapped Delay Source # | |
Source Delay Source # | |
Mutate Delay Source # | |
Delay ~ t => Rewrapped Delay t Source # | |
Defined in Verismith.Verilog.AST | |
type Rep Delay Source # | |
Defined in Verismith.Verilog.AST | |
type Unwrapped Delay Source # | |
Defined in Verismith.Verilog.AST |
Verilog syntax for an event, such as @x
, which is used for always blocks
EId !Identifier | |
EExpr !Expr | |
EAll | |
EPosEdge !Identifier | |
ENegEdge !Identifier | |
EOr !Event !Event | |
EComb !Event !Event |
Instances
Operators
data BinaryOperator Source #
Binary operators that are currently supported in the verilog generation.
BinPlus | + |
BinMinus | - |
BinTimes | * |
BinDiv | / |
BinMod | % |
BinEq | == |
BinNEq | != |
BinCEq | === |
BinCNEq | !== |
BinLAnd | && |
BinLOr | || |
BinLT | < |
BinLEq | <= |
BinGT | > |
BinGEq | >= |
BinAnd | & |
BinOr | | |
BinXor | ^ |
BinXNor | ^~ |
BinXNorInv | ~^ |
BinPower | ** |
BinLSL | << |
BinLSR | >> |
BinASL | <<< |
BinASR | >>> |
Instances
data UnaryOperator Source #
Unary operators that are currently supported by the generator.
Instances
Task
Task | |
|
Instances
Eq Task Source # | |
Data Task Source # | |
Defined in Verismith.Verilog.AST gfoldl :: (forall d b. Data d => c (d -> b) -> d -> c b) -> (forall g. g -> c g) -> Task -> c Task # gunfold :: (forall b r. Data b => c (b -> r) -> c r) -> (forall r. r -> c r) -> Constr -> c Task # dataTypeOf :: Task -> DataType # dataCast1 :: Typeable t => (forall d. Data d => c (t d)) -> Maybe (c Task) # dataCast2 :: Typeable t => (forall d e. (Data d, Data e) => c (t d e)) -> Maybe (c Task) # gmapT :: (forall b. Data b => b -> b) -> Task -> Task # gmapQl :: (r -> r' -> r) -> r -> (forall d. Data d => d -> r') -> Task -> r # gmapQr :: (r' -> r -> r) -> r -> (forall d. Data d => d -> r') -> Task -> r # gmapQ :: (forall d. Data d => d -> u) -> Task -> [u] # gmapQi :: Int -> (forall d. Data d => d -> u) -> Task -> u # gmapM :: Monad m => (forall d. Data d => d -> m d) -> Task -> m Task # gmapMp :: MonadPlus m => (forall d. Data d => d -> m d) -> Task -> m Task # gmapMo :: MonadPlus m => (forall d. Data d => d -> m d) -> Task -> m Task # | |
Ord Task Source # | |
Show Task Source # | |
Generic Task Source # | |
NFData Task Source # | |
Defined in Verismith.Verilog.AST | |
Source Task Source # | |
Mutate Task Source # | |
type Rep Task Source # | |
Defined in Verismith.Verilog.AST type Rep Task = D1 (MetaData "Task" "Verismith.Verilog.AST" "verismith-0.5.0.0-inplace" False) (C1 (MetaCons "Task" PrefixI True) (S1 (MetaSel (Just "_taskName") SourceUnpack SourceStrict DecidedStrict) (Rec0 Identifier) :*: S1 (MetaSel (Just "_taskExpr") NoSourceUnpackedness NoSourceStrictness DecidedLazy) (Rec0 [Expr]))) |
Left hand side value
Type that represents the left hand side of an assignment, which can be a concatenation such as in:
{a, b, c} = 32'h94238;
RegId | |
| |
RegExpr | |
| |
RegSize | |
| |
RegConcat | |
Instances
Eq LVal Source # | |
Data LVal Source # | |
Defined in Verismith.Verilog.AST gfoldl :: (forall d b. Data d => c (d -> b) -> d -> c b) -> (forall g. g -> c g) -> LVal -> c LVal # gunfold :: (forall b r. Data b => c (b -> r) -> c r) -> (forall r. r -> c r) -> Constr -> c LVal # dataTypeOf :: LVal -> DataType # dataCast1 :: Typeable t => (forall d. Data d => c (t d)) -> Maybe (c LVal) # dataCast2 :: Typeable t => (forall d e. (Data d, Data e) => c (t d e)) -> Maybe (c LVal) # gmapT :: (forall b. Data b => b -> b) -> LVal -> LVal # gmapQl :: (r -> r' -> r) -> r -> (forall d. Data d => d -> r') -> LVal -> r # gmapQr :: (r' -> r -> r) -> r -> (forall d. Data d => d -> r') -> LVal -> r # gmapQ :: (forall d. Data d => d -> u) -> LVal -> [u] # gmapQi :: Int -> (forall d. Data d => d -> u) -> LVal -> u # gmapM :: Monad m => (forall d. Data d => d -> m d) -> LVal -> m LVal # gmapMp :: MonadPlus m => (forall d. Data d => d -> m d) -> LVal -> m LVal # gmapMo :: MonadPlus m => (forall d. Data d => d -> m d) -> LVal -> m LVal # | |
Ord LVal Source # | |
Show LVal Source # | |
IsString LVal Source # | |
Defined in Verismith.Verilog.AST fromString :: String -> LVal # | |
Generic LVal Source # | |
NFData LVal Source # | |
Defined in Verismith.Verilog.AST | |
Source LVal Source # | |
Mutate LVal Source # | |
type Rep LVal Source # | |
Defined in Verismith.Verilog.AST type Rep LVal = D1 (MetaData "LVal" "Verismith.Verilog.AST" "verismith-0.5.0.0-inplace" False) ((C1 (MetaCons "RegId" PrefixI True) (S1 (MetaSel (Just "_regId") SourceUnpack SourceStrict DecidedStrict) (Rec0 Identifier)) :+: C1 (MetaCons "RegExpr" PrefixI True) (S1 (MetaSel (Just "_regExprId") SourceUnpack SourceStrict DecidedStrict) (Rec0 Identifier) :*: S1 (MetaSel (Just "_regExpr") NoSourceUnpackedness SourceStrict DecidedStrict) (Rec0 Expr))) :+: (C1 (MetaCons "RegSize" PrefixI True) (S1 (MetaSel (Just "_regSizeId") SourceUnpack SourceStrict DecidedStrict) (Rec0 Identifier) :*: S1 (MetaSel (Just "_regSizeRange") SourceUnpack SourceStrict DecidedStrict) (Rec0 Range)) :+: C1 (MetaCons "RegConcat" PrefixI True) (S1 (MetaSel (Just "_regConc") NoSourceUnpackedness NoSourceStrictness DecidedLazy) (Rec0 [Expr])))) |
Ports
Different port direction that are supported in Verilog.
PortIn | Input direction for port ( |
PortOut | Output direction for port ( |
PortInOut | Inout direction for port ( |
Instances
Eq PortDir Source # | |
Data PortDir Source # | |
Defined in Verismith.Verilog.AST gfoldl :: (forall d b. Data d => c (d -> b) -> d -> c b) -> (forall g. g -> c g) -> PortDir -> c PortDir # gunfold :: (forall b r. Data b => c (b -> r) -> c r) -> (forall r. r -> c r) -> Constr -> c PortDir # toConstr :: PortDir -> Constr # dataTypeOf :: PortDir -> DataType # dataCast1 :: Typeable t => (forall d. Data d => c (t d)) -> Maybe (c PortDir) # dataCast2 :: Typeable t => (forall d e. (Data d, Data e) => c (t d e)) -> Maybe (c PortDir) # gmapT :: (forall b. Data b => b -> b) -> PortDir -> PortDir # gmapQl :: (r -> r' -> r) -> r -> (forall d. Data d => d -> r') -> PortDir -> r # gmapQr :: (r' -> r -> r) -> r -> (forall d. Data d => d -> r') -> PortDir -> r # gmapQ :: (forall d. Data d => d -> u) -> PortDir -> [u] # gmapQi :: Int -> (forall d. Data d => d -> u) -> PortDir -> u # gmapM :: Monad m => (forall d. Data d => d -> m d) -> PortDir -> m PortDir # gmapMp :: MonadPlus m => (forall d. Data d => d -> m d) -> PortDir -> m PortDir # gmapMo :: MonadPlus m => (forall d. Data d => d -> m d) -> PortDir -> m PortDir # | |
Ord PortDir Source # | |
Show PortDir Source # | |
Generic PortDir Source # | |
NFData PortDir Source # | |
Defined in Verismith.Verilog.AST | |
Source PortDir Source # | |
Mutate PortDir Source # | |
type Rep PortDir Source # | |
Defined in Verismith.Verilog.AST |
Currently, only wire
and reg
are supported, as the other net types are
not that common and not a priority.
Instances
Eq PortType Source # | |
Data PortType Source # | |
Defined in Verismith.Verilog.AST gfoldl :: (forall d b. Data d => c (d -> b) -> d -> c b) -> (forall g. g -> c g) -> PortType -> c PortType # gunfold :: (forall b r. Data b => c (b -> r) -> c r) -> (forall r. r -> c r) -> Constr -> c PortType # toConstr :: PortType -> Constr # dataTypeOf :: PortType -> DataType # dataCast1 :: Typeable t => (forall d. Data d => c (t d)) -> Maybe (c PortType) # dataCast2 :: Typeable t => (forall d e. (Data d, Data e) => c (t d e)) -> Maybe (c PortType) # gmapT :: (forall b. Data b => b -> b) -> PortType -> PortType # gmapQl :: (r -> r' -> r) -> r -> (forall d. Data d => d -> r') -> PortType -> r # gmapQr :: (r' -> r -> r) -> r -> (forall d. Data d => d -> r') -> PortType -> r # gmapQ :: (forall d. Data d => d -> u) -> PortType -> [u] # gmapQi :: Int -> (forall d. Data d => d -> u) -> PortType -> u # gmapM :: Monad m => (forall d. Data d => d -> m d) -> PortType -> m PortType # gmapMp :: MonadPlus m => (forall d. Data d => d -> m d) -> PortType -> m PortType # gmapMo :: MonadPlus m => (forall d. Data d => d -> m d) -> PortType -> m PortType # | |
Ord PortType Source # | |
Defined in Verismith.Verilog.AST | |
Show PortType Source # | |
Generic PortType Source # | |
NFData PortType Source # | |
Defined in Verismith.Verilog.AST | |
Source PortType Source # | |
Mutate PortType Source # | |
type Rep PortType Source # | |
Port declaration. It contains information about the type of the port, the size, and the port name. It used to also contain information about if it was an input or output port. However, this is not always necessary and was more cumbersome than useful, as a lot of ports can be declared without input and output port.
This is now implemented inside ModDecl
itself, which uses a list of output
and input ports.
Port | |
|
Instances
Eq Port Source # | |
Data Port Source # | |
Defined in Verismith.Verilog.AST gfoldl :: (forall d b. Data d => c (d -> b) -> d -> c b) -> (forall g. g -> c g) -> Port -> c Port # gunfold :: (forall b r. Data b => c (b -> r) -> c r) -> (forall r. r -> c r) -> Constr -> c Port # dataTypeOf :: Port -> DataType # dataCast1 :: Typeable t => (forall d. Data d => c (t d)) -> Maybe (c Port) # dataCast2 :: Typeable t => (forall d e. (Data d, Data e) => c (t d e)) -> Maybe (c Port) # gmapT :: (forall b. Data b => b -> b) -> Port -> Port # gmapQl :: (r -> r' -> r) -> r -> (forall d. Data d => d -> r') -> Port -> r # gmapQr :: (r' -> r -> r) -> r -> (forall d. Data d => d -> r') -> Port -> r # gmapQ :: (forall d. Data d => d -> u) -> Port -> [u] # gmapQi :: Int -> (forall d. Data d => d -> u) -> Port -> u # gmapM :: Monad m => (forall d. Data d => d -> m d) -> Port -> m Port # gmapMp :: MonadPlus m => (forall d. Data d => d -> m d) -> Port -> m Port # gmapMo :: MonadPlus m => (forall d. Data d => d -> m d) -> Port -> m Port # | |
Ord Port Source # | |
Show Port Source # | |
Generic Port Source # | |
NFData Port Source # | |
Defined in Verismith.Verilog.AST | |
Source Port Source # | |
Mutate Port Source # | |
type Rep Port Source # | |
Defined in Verismith.Verilog.AST type Rep Port = D1 (MetaData "Port" "Verismith.Verilog.AST" "verismith-0.5.0.0-inplace" False) (C1 (MetaCons "Port" PrefixI True) ((S1 (MetaSel (Just "_portType") NoSourceUnpackedness SourceStrict DecidedStrict) (Rec0 PortType) :*: S1 (MetaSel (Just "_portSigned") NoSourceUnpackedness SourceStrict DecidedStrict) (Rec0 Bool)) :*: (S1 (MetaSel (Just "_portSize") SourceUnpack SourceStrict DecidedStrict) (Rec0 Range) :*: S1 (MetaSel (Just "_portName") SourceUnpack SourceStrict DecidedStrict) (Rec0 Identifier)))) |
Expression
Verilog expression, which can either be a primary expression, unary expression, binary operator expression or a conditional expression.
Number !BitVec | Number implementation containing the size and the value itself |
Id !Identifier | |
VecSelect !Identifier !Expr | |
RangeSelect !Identifier !Range | Symbols |
Concat !(NonEmpty Expr) | Bit-wise concatenation of expressions represented by braces. |
UnOp !UnaryOperator !Expr | |
BinOp !Expr !BinaryOperator !Expr | |
Cond !Expr !Expr !Expr | |
Appl !Identifier !Expr | |
Str !Text |
Instances
Constant expression, which are known before simulation at compile time.
ConstNum | |
ParamId | |
ConstConcat | |
| |
ConstUnOp | |
| |
ConstBinOp | |
| |
ConstCond | |
| |
ConstStr | |
Instances
constToExpr :: ConstExpr -> Expr Source #
exprToConst :: Expr -> ConstExpr Source #
Assignment
Assign | |
|
Instances
Eq Assign Source # | |
Data Assign Source # | |
Defined in Verismith.Verilog.AST gfoldl :: (forall d b. Data d => c (d -> b) -> d -> c b) -> (forall g. g -> c g) -> Assign -> c Assign # gunfold :: (forall b r. Data b => c (b -> r) -> c r) -> (forall r. r -> c r) -> Constr -> c Assign # toConstr :: Assign -> Constr # dataTypeOf :: Assign -> DataType # dataCast1 :: Typeable t => (forall d. Data d => c (t d)) -> Maybe (c Assign) # dataCast2 :: Typeable t => (forall d e. (Data d, Data e) => c (t d e)) -> Maybe (c Assign) # gmapT :: (forall b. Data b => b -> b) -> Assign -> Assign # gmapQl :: (r -> r' -> r) -> r -> (forall d. Data d => d -> r') -> Assign -> r # gmapQr :: (r' -> r -> r) -> r -> (forall d. Data d => d -> r') -> Assign -> r # gmapQ :: (forall d. Data d => d -> u) -> Assign -> [u] # gmapQi :: Int -> (forall d. Data d => d -> u) -> Assign -> u # gmapM :: Monad m => (forall d. Data d => d -> m d) -> Assign -> m Assign # gmapMp :: MonadPlus m => (forall d. Data d => d -> m d) -> Assign -> m Assign # gmapMo :: MonadPlus m => (forall d. Data d => d -> m d) -> Assign -> m Assign # | |
Ord Assign Source # | |
Show Assign Source # | |
Generic Assign Source # | |
NFData Assign Source # | |
Defined in Verismith.Verilog.AST | |
Mutate Assign Source # | |
type Rep Assign Source # | |
Defined in Verismith.Verilog.AST type Rep Assign = D1 (MetaData "Assign" "Verismith.Verilog.AST" "verismith-0.5.0.0-inplace" False) (C1 (MetaCons "Assign" PrefixI True) (S1 (MetaSel (Just "_assignReg") NoSourceUnpackedness SourceStrict DecidedStrict) (Rec0 LVal) :*: (S1 (MetaSel (Just "_assignDelay") NoSourceUnpackedness SourceStrict DecidedStrict) (Rec0 (Maybe Delay)) :*: S1 (MetaSel (Just "_assignExpr") NoSourceUnpackedness SourceStrict DecidedStrict) (Rec0 Expr)))) |
data ContAssign Source #
Instances
Statment
Statements in Verilog.
TimeCtrl | Time control ( |
| |
EventCtrl | |
| |
SeqBlock | Sequential block ( |
| |
BlockAssign | blocking assignment ( |
NonBlockAssign | Non blocking assignment ( |
TaskEnable | |
| |
SysTaskEnable | |
| |
CondStmnt | |
ForLoop | Loop bounds shall be statically computable for a for loop. |
Instances
Module
'module' module_identifier [list_of_ports] ';' { module_item } end_module
ModDecl | |
|
Instances
Module item which is the body of the module expression.
ModCA | |
ModInst | |
| |
Initial !Statement | |
Always !Statement | |
Decl | |
ParamDecl | |
LocalParamDecl | |
Instances
traverseModItem :: Applicative f => (Expr -> f Expr) -> ModItem -> f ModItem Source #
This is currently a type because direct module declaration should also be added:
mod a(.y(y1), .x1(x11), .x2(x22));
Instances
Eq ModConn Source # | |
Data ModConn Source # | |
Defined in Verismith.Verilog.AST gfoldl :: (forall d b. Data d => c (d -> b) -> d -> c b) -> (forall g. g -> c g) -> ModConn -> c ModConn # gunfold :: (forall b r. Data b => c (b -> r) -> c r) -> (forall r. r -> c r) -> Constr -> c ModConn # toConstr :: ModConn -> Constr # dataTypeOf :: ModConn -> DataType # dataCast1 :: Typeable t => (forall d. Data d => c (t d)) -> Maybe (c ModConn) # dataCast2 :: Typeable t => (forall d e. (Data d, Data e) => c (t d e)) -> Maybe (c ModConn) # gmapT :: (forall b. Data b => b -> b) -> ModConn -> ModConn # gmapQl :: (r -> r' -> r) -> r -> (forall d. Data d => d -> r') -> ModConn -> r # gmapQr :: (r' -> r -> r) -> r -> (forall d. Data d => d -> r') -> ModConn -> r # gmapQ :: (forall d. Data d => d -> u) -> ModConn -> [u] # gmapQi :: Int -> (forall d. Data d => d -> u) -> ModConn -> u # gmapM :: Monad m => (forall d. Data d => d -> m d) -> ModConn -> m ModConn # gmapMp :: MonadPlus m => (forall d. Data d => d -> m d) -> ModConn -> m ModConn # gmapMo :: MonadPlus m => (forall d. Data d => d -> m d) -> ModConn -> m ModConn # | |
Ord ModConn Source # | |
Show ModConn Source # | |
Generic ModConn Source # | |
NFData ModConn Source # | |
Defined in Verismith.Verilog.AST | |
Mutate ModConn Source # | |
type Rep ModConn Source # | |
Defined in Verismith.Verilog.AST type Rep ModConn = D1 (MetaData "ModConn" "Verismith.Verilog.AST" "verismith-0.5.0.0-inplace" False) (C1 (MetaCons "ModConn" PrefixI True) (S1 (MetaSel (Just "_modExpr") NoSourceUnpackedness SourceStrict DecidedStrict) (Rec0 Expr)) :+: C1 (MetaCons "ModConnNamed" PrefixI True) (S1 (MetaSel (Just "_modConnName") SourceUnpack SourceStrict DecidedStrict) (Rec0 Identifier) :*: S1 (MetaSel (Just "_modExpr") NoSourceUnpackedness SourceStrict DecidedStrict) (Rec0 Expr))) |
Useful Lenses and Traversals
Quote
verilog :: QuasiQuoter Source #
Quasiquoter for verilog, so that verilog can be written inline and be parsed to an AST at compile time.