| Copyright | (c) Marc Fontaine 2017 |
|---|---|
| License | BSD3 |
| Maintainer | Marc.Fontaine@gmx.de |
| Stability | experimental |
| Portability | GHC-only |
| Safe Haskell | Safe |
| Language | Haskell2010 |
Hardware.SiClock
Description
This is the main API.
- type Frequency = Rational
- type Divider = Rational
- data Config = Config {}
- defaultConfig :: Config
- defaultConfigEnv :: HasCallStack => IO Config
- testIO :: IO ()
- type Synth a = forall m. MonadIO m => SynthT Config m a
- runSynth :: HasCallStack => SynthT Config IO a -> IO a
- runSynthWith :: HasCallStack => Config -> SynthT Config IO a -> IO a
- askXtalFrequency :: Synth Frequency
- askMaxPLLFrequency :: Synth Frequency
- data PLL
- data CLK
- pllReset :: Synth ()
- clk0_On :: Synth ()
- clk0_Off :: Synth ()
- data DividerPair = DividerPair {}
- setDividers :: PLL -> CLK -> Frequency -> Synth DividerPair
- defaultDividers :: Frequency -> Synth DividerPair
- setPLLDivider :: PLL -> Divider -> Synth ()
- setPLLDivider_A :: Divider -> Synth ()
- setPLLDivider_B :: Divider -> Synth ()
- setCLKDivider :: CLK -> Word8 -> Divider -> Synth ()
- data CLK_Control_bits
- setCLKControl :: CLK -> [CLK_Control_bits] -> Synth ()
- setCLKControlRaw :: CLK -> Word8 -> Synth ()
- controlBitsToWord8 :: [CLK_Control_bits] -> Word8
- newtype DividerConf = DividerConf {}
- toDividerConf :: Word8 -> Divider -> DividerConf
- setDividerRaw :: DividerAddr hw => hw -> DividerConf -> Synth ()
- class DividerAddr a where
- _SI_CLK0_CONTROL :: Word8
- _SI_CLK1_CONTROL :: Word8
- _SI_CLK2_CONTROL :: Word8
- _SI_SYNTH_PLL_A :: Word8
- _SI_SYNTH_PLL_B :: Word8
- _SI_PLL_RESET :: Word8
- _SI_CLOCK_I2C_DEVICE :: String
- _SI_CLOCK_I2C_ADDRESS :: String
- _SI_CLOCK_XTAL_FREQUENCY :: String
- _SI_CLOCK_MAX_PLL_FREQUENCY :: String
Documentation
Constructors
| Config | |
Fields | |
defaultConfig :: Config Source #
The defaultConfig if no environment variables are set.
defaultConfigEnv :: HasCallStack => IO Config Source #
Check that defaultConfigEnv matches your hardware before you use it. Do not run any SiPLL code on a wrong i2c-bus, i.e. an internal I2C bus of your PC. (it might confuse and or wreck) your hardware. You can overwrite config values with the following ENV variables: SI_CLOCK_I2C_DEVICE SI_CLOCK_I2C_ADDRESS SI_CLOCK_XTAL_FREQUENCY SI_CLOCK_MAX_PLL_FREQUENCY
runSynth :: HasCallStack => SynthT Config IO a -> IO a Source #
Run the Synth monad with the config from defaultConfigEnv. | .i.e. reading Env
runSynthWith :: HasCallStack => Config -> SynthT Config IO a -> IO a Source #
Run the Synth monad with a custom configuration.
An IC has PLL_A and PLL_B.
An IC has up to 8 clocks. (CLK_0..CLK_7).
data DividerPair Source #
Constructors
| DividerPair | |
Fields
| |
Instances
setDividers :: PLL -> CLK -> Frequency -> Synth DividerPair Source #
Set PLL and Clock dividers for a frequency.
defaultDividers :: Frequency -> Synth DividerPair Source #
Compute a pair of good default pll and clk dividers. (clk divider is an integer)
setPLLDivider_A :: Divider -> Synth () Source #
Short for setPLLDivider PLL_A
setPLLDivider_B :: Divider -> Synth () Source #
Short for setPLLDivider PLL_B
setCLKDivider :: CLK -> Word8 -> Divider -> Synth () Source #
Setup a Clock divider. The rfield is passed as a plain Word8. (ToDo high level API for rfields).
data CLK_Control_bits Source #
Bits in the clock control registers.
Constructors
| CLK_on | |
| CLK_off | |
| CLK_fractional | |
| CLK_integer | |
| CLK_multiPLLA | |
| CLK_multiPLLB | |
| CLK_inverted | |
| CLK_XTAL | |
| CLK_CLKin | |
| CLK_multi | |
| CLK_DRV2 | |
| CLK_DRV4 | |
| CLK_DRV6 | |
| CLK_DRV8 |
Instances
setCLKControl :: CLK -> [CLK_Control_bits] -> Synth () Source #
controlBitsToWord8 :: [CLK_Control_bits] -> Word8 Source #
newtype DividerConf Source #
A DividerConf is basically the bytestring that configures a fractional divider.
Constructors
| DividerConf | |
Fields | |
Instances
toDividerConf :: Word8 -> Divider -> DividerConf Source #
Mangle a Divider and a rval into a DividerConf. This can be used to pre-compute all the math and to get the bits that define a divider.
setDividerRaw :: DividerAddr hw => hw -> DividerConf -> Synth () Source #
Setup some fractional divider with a pre-computed config. Using a pre-computed config might be faster or more convenient.
class DividerAddr a where Source #
Get address of the fractional divider.
Minimal complete definition
Methods
toDividerAddr :: a -> Word8 Source #
Instances
| DividerAddr Word8 Source # | Generic Address of fractional divider. |
| DividerAddr CLK Source # | Address of a Clock divider. |
| DividerAddr PLL Source # | Address of a PLL divider. |