Copyright | (c) David Cox 2024 |
---|---|
License | BSD-3-Clause |
Maintainer | standardsemiconductor@gmail.com |
Safe Haskell | None |
Language | Haskell2010 |
Synopsis
- core :: HiddenClockResetEnable dom => CoreConfig -> Signal dom (BitVector 32) -> FromCore dom
- defaultCoreConfig :: CoreConfig
- defaultPipeConfig :: PipeConfig
- data CoreConfig = CoreConfig {}
- data AluConfig
- newtype PipeConfig = PipeConfig {}
- data FromCore dom = FromCore {}
- data ToMem = ToMem {
- memAccess :: MemoryAccess
- memAddress :: BitVector 32
- memByteMask :: BitVector 4
- memWrite :: Maybe (BitVector 32)
- data MemoryAccess
Documentation
:: HiddenClockResetEnable dom | |
=> CoreConfig | core configuration |
-> Signal dom (BitVector 32) | core input, from memory/peripherals |
-> FromCore dom | core output |
RISC-V Core: RV32I
defaultPipeConfig :: PipeConfig Source #
Default pipeline configuration
startPC
= 0
data CoreConfig Source #
Core configuration
CoreConfig | |
|
Instances
Eq CoreConfig Source # | |
Defined in Lion.Core (==) :: CoreConfig -> CoreConfig -> Bool Source # (/=) :: CoreConfig -> CoreConfig -> Bool Source # | |
Show CoreConfig Source # | |
Generic CoreConfig Source # | |
Defined in Lion.Core from :: CoreConfig -> Rep CoreConfig x Source # to :: Rep CoreConfig x -> CoreConfig Source # | |
type Rep CoreConfig Source # | |
Defined in Lion.Core type Rep CoreConfig = D1 ('MetaData "CoreConfig" "Lion.Core" "lion-0.4.0.0-inplace" 'False) (C1 ('MetaCons "CoreConfig" 'PrefixI 'True) (S1 ('MetaSel ('Just "aluConfig") 'NoSourceUnpackedness 'NoSourceStrictness 'DecidedLazy) (Rec0 AluConfig) :*: S1 ('MetaSel ('Just "pipeConfig") 'NoSourceUnpackedness 'NoSourceStrictness 'DecidedLazy) (Rec0 PipeConfig))) |
ALU configuration
Hard | use hard adder and subtractor from iCE40 SB_MAC16 |
Soft | use generic adder and subtractor: (+) and (-) |
newtype PipeConfig Source #
Pipeline configuration
Instances
Eq PipeConfig Source # | |
Defined in Lion.Pipe (==) :: PipeConfig -> PipeConfig -> Bool Source # (/=) :: PipeConfig -> PipeConfig -> Bool Source # | |
Show PipeConfig Source # | |
Generic PipeConfig Source # | |
Defined in Lion.Pipe from :: PipeConfig -> Rep PipeConfig x Source # to :: Rep PipeConfig x -> PipeConfig Source # | |
type Rep PipeConfig Source # | |
Defined in Lion.Pipe type Rep PipeConfig = D1 ('MetaData "PipeConfig" "Lion.Pipe" "lion-0.4.0.0-inplace" 'True) (C1 ('MetaCons "PipeConfig" 'PrefixI 'True) (S1 ('MetaSel ('Just "startPC") 'NoSourceUnpackedness 'NoSourceStrictness 'DecidedLazy) (Rec0 (BitVector 32)))) |
Core outputs
Memory bus
ToMem | |
|
Instances
Eq ToMem Source # | |
Show ToMem Source # | |
Generic ToMem Source # | |
NFDataX ToMem Source # | |
type Rep ToMem Source # | |
Defined in Lion.Pipe type Rep ToMem = D1 ('MetaData "ToMem" "Lion.Pipe" "lion-0.4.0.0-inplace" 'False) (C1 ('MetaCons "ToMem" 'PrefixI 'True) ((S1 ('MetaSel ('Just "memAccess") 'NoSourceUnpackedness 'NoSourceStrictness 'DecidedLazy) (Rec0 MemoryAccess) :*: S1 ('MetaSel ('Just "memAddress") 'NoSourceUnpackedness 'NoSourceStrictness 'DecidedLazy) (Rec0 (BitVector 32))) :*: (S1 ('MetaSel ('Just "memByteMask") 'NoSourceUnpackedness 'NoSourceStrictness 'DecidedLazy) (Rec0 (BitVector 4)) :*: S1 ('MetaSel ('Just "memWrite") 'NoSourceUnpackedness 'NoSourceStrictness 'DecidedLazy) (Rec0 (Maybe (BitVector 32)))))) |
data MemoryAccess Source #
Memory access - Lion has a shared instruction/memory bus
Instances
Eq MemoryAccess Source # | |
Defined in Lion.Pipe (==) :: MemoryAccess -> MemoryAccess -> Bool Source # (/=) :: MemoryAccess -> MemoryAccess -> Bool Source # | |
Show MemoryAccess Source # | |
Generic MemoryAccess Source # | |
Defined in Lion.Pipe from :: MemoryAccess -> Rep MemoryAccess x Source # to :: Rep MemoryAccess x -> MemoryAccess Source # | |
NFDataX MemoryAccess Source # | |
Defined in Lion.Pipe deepErrorX :: String -> MemoryAccess Source # hasUndefined :: MemoryAccess -> Bool Source # ensureSpine :: MemoryAccess -> MemoryAccess Source # rnfX :: MemoryAccess -> () Source # | |
type Rep MemoryAccess Source # | |