Clash has synchronous Signals in the form of:

Signal (dom :: Domain) a

Where a is the type of the value of the Signal, for example Int or Bool, and dom is the clock- (and reset-) domain to which the memory elements manipulating these Signals belong.

The type-parameter, dom, is of the kind Domain - a simple string. That string refers to a single synthesis domain. A synthesis domain describes the behavior of certain aspects of memory elements in it.

• NB: "Bad things"™ happen when you actually use a clock period of 0, so do not do that!
• NB: You should be judicious using a clock with period of 1 as you can never create a clock that goes any faster!
• NB: For the best compatibility make sure your period is divisible by 2, because some VHDL simulators don't support fractions of picoseconds.
• NB: Whether System has good defaults depends on your target platform. Check out IntelSystem and XilinxSystem too!

Signals have the type role

>>> :i Signal
type role Signal nominal representational
...

as it is safe to coerce the underlying value of a signal, but not safe to coerce a signal between different synthesis domains.

See the module documentation of Clash.Signal for more information about domains.

The in part of an inout port. BiSignalIn has the type role

>>> :i BiSignalIn
type role BiSignalIn nominal nominal nominal
...

as it is not safe to coerce the default behaviour, synthesis domain or width of the data in the signal.

The out part of an inout port

Wraps (multiple) writing signals. The semantics are such that only one of the signals may write at a single time step.

BiSignalOut has the type role

>>> :i BiSignalOut
type role BiSignalOut nominal nominal nominal
...

as it is not safe to coerce the default behaviour, synthesis domain or width of the data in the signal.

Used to specify the default behavior of a "BiSignal" in Haskell simulation, i.e. what value is read when no value is being written to it.

A KnownDomain constraint indicates that a circuit's behavior depends on some properties of a domain. See DomainConfiguration for more information.

Determines clock edge memory elements are sensitive to. Not yet implemented.

Singleton version of ActiveEdge

Singleton version of ResetKind

Determines the value for which a reset line is considered "active"

Singleton version of ResetPolarity

A domain with a name (Domain). Configures the behavior of various aspects of a circuits. See the documentation of this record's field types for more information on the options.

See module documentation of Clash.Explicit.Signal for more information on how to create custom synthesis domains.

Singleton version of DomainConfiguration

Convenience type to help to extract a period from a domain. Example usage:

myFunc :: (KnownDomain dom, DomainPeriod dom ~ 6000) => ...

Convenience type to help to extract the active edge from a domain. Example usage:

myFunc :: (KnownDomain dom, DomainActiveEdge dom ~ 'Rising) => ...

Convenience type to help to extract the reset synchronicity from a domain. Example usage:

myFunc :: (KnownDomain dom, DomainResetKind dom ~ 'Synchronous) => ...

Convenience type to help to extract the initial value behavior from a domain. Example usage:

myFunc :: (KnownDomain dom, DomainInitBehavior dom ~ 'Defined) => ...

Convenience type to help to extract the reset polarity from a domain. Example usage:

myFunc :: (KnownDomain dom, DomainResetPolarity dom ~ 'ActiveHigh) => ...

Convenience type to constrain a domain to have synchronous resets. Example usage:

myFunc :: HasSynchronousReset dom => ...

Using this type implies KnownDomain.

Click here for usage hints

Convenience type to constrain a domain to have asynchronous resets. Example usage:

myFunc :: HasAsynchronousReset dom => ...

Using this type implies KnownDomain.

Click here for usage hints

Convenience type to constrain a domain to have initial values. Example usage:

myFunc :: HasDefinedInitialValues dom => ...

Using this type implies KnownDomain.

Note that there is no UnknownInitialValues dom as a component that works without initial values will also work if it does have them.

Click here for usage hints

Gets time in Picoseconds from time in Seconds

Gets time in Picoseconds from time in Milliseconds

Gets time in Picoseconds from time in Microseconds

Gets time in Picoseconds from time in Nanoseconds

Gets time in Picoseconds from time in picoseconds, essentially id

The domain's clock frequency in hertz, calculated based on the period stored in picoseconds. This might lead to rounding errors.

Converts a frequency in hertz to a period in picoseconds. This might lead to rounding errors.

Converts a period in picoseconds to a frequency in hertz. This might lead to rounding errors.

Number of clock cycles required at the clock frequency of dom before a minimum period has passed

Number of clock cycles required at the clock frequency of dom before a minimum period has passed. The same as PeriodToCycles.

A clock (and reset) dom with clocks running at 100 MHz. Memory elements respond to the rising edge of the clock, and asynchronously to changes in reset signals. It has defined initial values, and active-high resets.

See module documentation of Clash.Explicit.Signal for more information on how to create custom synthesis domains.

A clock (and reset) dom with clocks running at 100 MHz. Memory elements respond to the rising edge of the clock, and synchronously to changes in reset signals. It has defined initial values, and active-high resets.

See module documentation of Clash.Explicit.Signal for more information on how to create custom synthesis domains.

A clock (and reset) dom with clocks running at 100 MHz. Memory elements respond to the rising edge of the clock, and asynchronously to changes in reset signals. It has defined initial values, and active-high resets.

See module documentation of Clash.Explicit.Signal for more information on how to create custom synthesis domains.

Convenience value to allow easy "subclassing" of System domain. Should be used in combination with createDomain. For example, if you just want to change the period but leave all other settings intact use:

createDomain vSystem{vName="System10", vPeriod=10}

Convenience value to allow easy "subclassing" of IntelSystem domain. Should be used in combination with createDomain. For example, if you just want to change the period but leave all other settings intact use:

createDomain vIntelSystem{vName="Intel10", vPeriod=10}

Convenience value to allow easy "subclassing" of XilinxSystem domain. Should be used in combination with createDomain. For example, if you just want to change the period but leave all other settings intact use:

createDomain vXilinxSystem{vName="Xilinx10", vPeriod=10}

Same as SDomainConfiguration but allows for easy updates through record update syntax. Should be used in combination with vDomain and createDomain. Example:

createDomain (knownVDomain @System){vName="System10", vPeriod=10}

This duplicates the settings in the System domain, replaces the name and period, and creates an instance for it. As most users often want to update the system domain, a shortcut is available in the form:

createDomain vSystem{vName="System10", vPeriod=10}

Convert SDomainConfiguration to VDomainConfiguration. Should be used in combination with createDomain only.

Convenience method to express new domains in terms of others.

createDomain (knownVDomain @System){vName="System10", vPeriod=10}

This duplicates the settings in the System domain, replaces the name and period, and creates an instance for it. As most users often want to update the system domain, a shortcut is available in the form:

createDomain vSystem{vName="System10", vPeriod=10}

The function will create two extra identifiers. The first:

type System10 = ..

You can use that as the dom to Clocks/Resets/Enables/Signals. For example: Signal System10 Int. Additionally, it will create a VDomainConfiguration that you can use in later calls to createDomain:

vSystem10 = knownVDomain @System10

It will also make System10 an instance of KnownDomain.

If either identifier is already in scope it will not be generated a second time. Note: This can be useful for example when documenting a new domain:

-- | Here is some documentation for CustomDomain
type CustomDomain = ("CustomDomain" :: Domain)

-- | Here is some documentation for vCustomDomain
createDomain vSystem{vName="CustomDomain"}

Like 'knownDomain but yields a VDomainConfiguration. Should only be used in combination with createDomain.

Get the clock period from a KnownDomain context

Get ActiveEdge from a KnownDomain context. Example usage:

f :: forall dom . KnownDomain dom => ....
f a b c =
  case activeEdge @dom of
    SRising -> foo
    SFalling -> bar

Get ResetKind from a KnownDomain context. Example usage:

f :: forall dom . KnownDomain dom => ....
f a b c =
  case resetKind @dom of
    SAsynchronous -> foo
    SSynchronous -> bar

Get InitBehavior from a KnownDomain context. Example usage:

f :: forall dom . KnownDomain dom => ....
f a b c =
  case initBehavior @dom of
    SDefined -> foo
    SUnknown -> bar

Get ResetPolarity from a KnownDomain context. Example usage:

f :: forall dom . KnownDomain dom => ....
f a b c =
  case resetPolarity @dom of
    SActiveHigh -> foo
    SActiveLow -> bar

A signal of booleans, indicating whether a component is enabled. No special meaning is implied, it's up to the component itself to decide how to respond to its enable line. It is used throughout Clash as a global enable signal.

Convert a signal of bools to an Enable construct

Convert Enable construct to its underlying representation: a signal of bools.

Enable generator for some domain. Is simply always True.

A clock signal belonging to a domain named dom.

A differential clock signal belonging to a domain named dom. The clock input of a design with such an input has two ports which are in antiphase. The first input is the positive phase, the second the negative phase. When using makeTopEntity, the names of the inputs will end in _p and _n respectively.

To create a differential clock in a test bench, you can use clockToDiffClock.

Calculate the frequency in Hz, given the period in ps

I.e., to calculate the clock frequency of a clock with a period of 5000 ps:

>>> periodToHz 5000
2.0e8

Note that if p in periodToHz (fromIntegral p) is negative, fromIntegral will give an Underflow :: ArithException without a call stack, making debugging cumbersome.

Before Clash 1.8, this function always returned a Ratio Natural. To get the old behavior of this function, use a type application:

>>> periodToHz @(Ratio Natural) 5000
200000000 % 1

NB: This function is not synthesizable

Calculate the period in ps, given a frequency in Hz

I.e., to calculate the clock period for a circuit to run at 240 MHz we get

>>> hzToPeriod 240e6
4166

If the value hzToPeriod is applied to is not of the type Ratio Natural, you can use hzToPeriod (realToFrac f). Note that if f is negative, realToFrac will give an Underflow :: ArithException without a call stack, making debugging cumbersome.

Before Clash 1.8, this function always returned a Natural. To get the old behavior of this function, use a type application:

>>> hzToPeriod @Natural 240e6
4166

• NB: This function is not synthesizable
• NB: This function is lossy. I.e., periodToHz . hzToPeriod /= id.

The unsafeSynchronizer function is a primitive that must be used to connect one clock domain to the other, and will be synthesized to a (bundle of) wire(s) in the eventual circuit. This function should only be used as part of a proper synchronization component, such as the following dual flip-flop synchronizer:

dualFlipFlop
  :: Clock domA
  -> Clock domB
  -> Enable domA
  -> Enable domB
  -> Bit
  -> Signal domA Bit
  -> Signal domB Bit
dualFlipFlop clkA clkB enA enB dflt =
  delay clkB enB dflt . delay clkB enB dflt . unsafeSynchronizer clkA clkB

The unsafeSynchronizer works in such a way that, given 2 clocks:

createDomain vSystem{vName="Dom7", vPeriod=7}

clk7 :: Clock Dom7
clk7 = clockGen

en7 :: Enable Dom7
en7 = enableGen

and

createDomain vSystem{vName="Dom2", vPeriod=2}

clk2 :: Clock Dom2
clk2 = clockGen

en2 :: Enable Dom2
en2 = enableGen

Oversampling followed by compression is the identity function plus 2 initial values:

delay clkB enB dflt $
unsafeSynchronizer clkA clkB $
delay clkA enA dflt $
unsafeSynchronizer clkB clkA $
delay clkB enB s

==

dflt :- dflt :- s

Something we can easily observe:

oversampling clkA clkB enA enB dflt =
  delay clkB enB dflt
    . unsafeSynchronizer clkA clkB
    . delay clkA enA dflt
almostId clkA clkB enA enB dflt =
  delay clkB enB dflt
    . unsafeSynchronizer clkA clkB
    . delay clkA enA dflt
    . unsafeSynchronizer clkB clkA
    . delay clkB enB dflt

>>> sampleN 37 (oversampling clk7 clk2 en7 en2 0 (fromList [(1::Int)..10]))
[0,0,1,1,1,2,2,2,2,3,3,3,4,4,4,4,5,5,5,6,6,6,6,7,7,7,8,8,8,8,9,9,9,10,10,10,10]
>>> sampleN 12 (almostId clk2 clk7 en2 en7 0 (fromList [(1::Int)..10]))
[0,0,1,2,3,4,5,6,7,8,9,10]

Same as unsafeSynchronizer, but with manually supplied clock periods.

Note: this unsafeSynchronizer is defined to be consistent with the vhdl and verilog implementations however as only synchronous signals are represented in Clash this cannot be done precisely and can lead to odd behavior. For example,

sample $ unsafeSynchronizer @Dom2 @Dom7 . unsafeSynchronizer @Dom7 @Dom2 $ fromList [0..10]
> [0,4,4,4,7,7,7,7,11,11,11..

is quite different from the identity,

sample $ fromList [0..10]
> [0,1,2,3,4,5,6,7,8,9,10..

with values appearing from the "future".

A reset signal belonging to a domain called dom.

The underlying representation of resets is Bool.

unsafeToReset is unsafe. For asynchronous resets it is unsafe because it can introduce combinatorial loops. In case of synchronous resets it can lead to meta-stability issues in the presence of asynchronous resets.

NB: You probably want to use unsafeFromActiveLow or unsafeFromActiveHigh.

unsafeFromReset is unsafe because it can introduce:

• meta-stability

For asynchronous resets it is unsafe because it can cause combinatorial loops. In case of synchronous resets it can lead to meta-stability in the presence of asynchronous resets.

NB: You probably want to use unsafeToActiveLow or unsafeToActiveHigh.

Convert a reset to an active high reset. Has no effect if reset is already an active high reset. Is unsafe because it can introduce:

• meta-stability

For asynchronous resets it is unsafe because it can cause combinatorial loops. In case of synchronous resets it can lead to meta-stability in the presence of asynchronous resets.

Convert a reset to an active low reset. Has no effect if reset is already an active low reset. It is unsafe because it can introduce:

• meta-stability

For asynchronous resets it is unsafe because it can cause combinatorial loops. In case of synchronous resets it can lead to meta-stability in the presence of asynchronous resets.

Interpret a signal of bools as an active high reset and convert it to a reset signal corresponding to the domain's setting.

For asynchronous resets it is unsafe because it can cause combinatorial loops. In case of synchronous resets it can lead to meta-stability in the presence of asynchronous resets.

Interpret a signal of bools as an active low reset and convert it to a reset signal corresponding to the domain's setting.

For asynchronous resets it is unsafe because it can cause combinatorial loops. In case of synchronous resets it can lead to meta-stability in the presence of asynchronous resets.

Merge enable signal with signal of bools by applying the boolean AND operation.

Special version of delay that doesn't take enable signals of any kind. Initial value will be undefined.

"delay clk s" delays the values in Signal s for once cycle, the value at time 0 is dflt.

>>> sampleN 3 (delay systemClockGen enableGen 0 (fromList [1,2,3,4]))
[0,1,2]

Version of delay that only updates when its third argument is a Just value.

>>> let input = fromList [Just 1, Just 2, Nothing, Nothing, Just 5, Just 6, Just (7::Int)]
>>> sampleN 7 (delayMaybe systemClockGen enableGen 0 input)
[0,1,2,2,2,5,6]

Version of delay that only updates when its third argument is asserted.

>>> let input = fromList [1,2,3,4,5,6,7::Int]
>>> let enable = fromList [True,True,False,False,True,True,True]
>>> sampleN 7 (delayEn systemClockGen enableGen 0 enable input)
[0,1,2,2,2,5,6]

"register clk rst en i s" delays the values in Signal s for one cycle, and sets the value to i the moment the reset becomes False.

>>> sampleN 5 (register systemClockGen resetGen enableGen 8 (fromList [1,1,2,3,4]))
[8,8,1,2,3]

Version of register that only updates its content when its fourth argument is a Just value. So given:

sometimes1 clk rst en = s where
  s = register clk rst en Nothing (switch <$> s)

  switch Nothing = Just 1
  switch _       = Nothing

countSometimes clk rst en = s where
  s     = regMaybe clk rst en 0 (plusM (pure <$> s) (sometimes1 clk rst en))
  plusM = liftA2 (liftA2 (+))

We get:

>>> sampleN 9 (sometimes1 systemClockGen resetGen enableGen)
[Nothing,Nothing,Just 1,Nothing,Just 1,Nothing,Just 1,Nothing,Just 1]
>>> sampleN 9 (count systemClockGen resetGen enableGen)
[0,0,0,1,1,2,2,3,3]

Version of register that only updates its content when its fourth argument is asserted. So given:

oscillate clk rst en = let s = register clk rst en False (not <$> s) in s
count clk rst en     = let s = 'regEn clk rst en 0 (oscillate clk rst en) (s + 1) in s

We get:

>>> sampleN 9 (oscillate systemClockGen resetGen enableGen)
[False,False,True,False,True,False,True,False,True]
>>> sampleN 9 (count systemClockGen resetGen enableGen)
[0,0,0,1,1,2,2,3,3]

The above type is a generalization for:

mux :: Signal Bool -> Signal a -> Signal a -> Signal a