clash-prelude
Copyright(C) 2017 Google Inc
2019 Myrtle Software Ltd
2025 QBayLogic B.V.
LicenseBSD2 (see the file LICENSE)
MaintainerQBayLogic B.V. <devops@qbaylogic.com>
Safe HaskellNone
LanguageHaskell2010

Clash.Explicit.DDR

Contents

Description

We simulate DDR signal by using Signals which have exactly half the period (or double the speed) of our normal Signals.

The primitives in this module can be used to produce or consume DDR signals.

DDR signals are not meant to be used internally in a design, but only to communicate with the outside world.

In some cases hardware specific DDR IN registers can be inferred by synthesis tools from these generic primitives. But to be sure your design will synthesize to dedicated hardware resources use the functions from Clash.Intel.DDR or Clash.Xilinx.DDR.

Synopsis

Documentation

ddrIn Source #

Arguments

:: (HasCallStack, NFDataX a, KnownConfiguration fast ('DomainConfiguration fast fPeriod edge reset init polarity), KnownConfiguration slow ('DomainConfiguration slow (2 * fPeriod) edge reset init polarity)) 
=> Clock slow

clock

-> Reset slow

reset

-> Enable slow 
-> (a, a, a)

reset values

-> Signal fast a

DDR input signal

-> Signal slow (a, a)

normal speed output pairs

DDR input primitive

Consumes a DDR input signal and produces a regular signal containing a pair of values.

>>> printX $ sampleN 5 $ ddrIn systemClockGen systemResetGen enableGen (-1,-2,-3) (fromList [0..10] :: Signal "Fast" Int)
[(-1,-2),(-1,-2),(-3,2),(3,4),(5,6)]

ddrOut Source #

Arguments

:: (HasCallStack, NFDataX a, KnownConfiguration fast ('DomainConfiguration fast fPeriod edge reset init polarity), KnownConfiguration slow ('DomainConfiguration slow (2 * fPeriod) edge reset init polarity)) 
=> Clock slow 
-> Reset slow 
-> Enable slow 
-> a

reset value

-> Signal slow (a, a)

Normal speed input pairs

-> Signal fast a

DDR output signal

DDR output primitive

Produces a DDR output signal from a normal signal of pairs of input.

>>> sampleN 7 (ddrOut systemClockGen systemResetGen enableGen (-1) (fromList [(0,1),(2,3),(4,5)]) :: Signal "Fast" Int)
[-1,-1,-1,2,3,4,5]

ddrForwardClock Source #

Arguments

:: forall domDDR domOut domIn. KnownDomain domOut 
=> DomainPeriod domIn ~ DomainPeriod domOut 
=> DomainPeriod domIn ~ (2 * DomainPeriod domDDR) 
=> Clock domIn 
-> Reset domIn 
-> Enable domIn 
-> Maybe Bit

idle: Output value when Enable is deasserted

-> Maybe Bit

phase: Value to output at active edge of incoming clock

-> (Clock domIn -> Reset domIn -> Enable domIn -> Signal domIn (Bit, Bit) -> Signal domDDR Bit)

ddrOut primitive to use

-> Clock domOut 

Use a DDR output primitive to forward a clock to an output pin

This function allows outputting a clock signal on a DDR-capable output pin. As with the DDR output primitive itself, the created clock cannot be used internally in the design.

The ddrOut primitive passed in will always have its enable asserted. If the Enable input of ddrForwardClock is deasserted, the data inputs of the ddrOut primitive will switch to achieve the desired output signal. This is because the behavior of the enable input of the DDR primitive differs between vendor-specific primitives.

The Reset input of this function is passed on to the ddrOut primitive and not otherwise used by ddrForwardClock.

With the phase argument, the phase relation between input and output clock can be defined. With the argument Nothing, the clocks are in phase: the active edge of the output clock is on the active edge of the input clock, even if the domains differ on what the active edge is.

With the idle argument, the output level when the Enable input is deasserted can be defined. With Nothing, it will be 0 for a clock with the rising edge as the active edge, and 1 for a clock with the falling edge as the active edge.

NB: The deassertion of the Enable input or the assertion of the Reset input is not faithfully simulated in Haskell simulation: Haskell simulation of a Clash design has clocks that always run. The generated HDL will actually output an idle state when Enable is deasserted (and the reset depends on the ddrOut primitive used).

Internal

ddrIn# :: forall a slow fast fPeriod polarity edge reset init. (HasCallStack, NFDataX a, KnownConfiguration fast ('DomainConfiguration fast fPeriod edge reset init polarity), KnownConfiguration slow ('DomainConfiguration slow (2 * fPeriod) edge reset init polarity)) => Clock slow -> Reset slow -> Enable slow -> a -> a -> a -> Signal fast a -> Signal slow (a, a) Source #

ddrOut# :: (HasCallStack, NFDataX a, KnownConfiguration fast ('DomainConfiguration fast fPeriod edge reset init polarity), KnownConfiguration slow ('DomainConfiguration slow (2 * fPeriod) edge reset init polarity)) => Clock slow -> Reset slow -> Enable slow -> a -> Signal slow a -> Signal slow a -> Signal fast a Source #

ddrForwardClock# :: KnownDomain domOut => DomainPeriod domIn ~ DomainPeriod domOut => DomainPeriod domIn ~ (2 * DomainPeriod domDDR) => Clock domIn -> Signal domDDR Bit -> Clock domOut Source #