clash-prelude-1.8.0: Clash: a functional hardware description language - Prelude library
Copyright(C) 2023 QBayLogic B.V.
LicenseBSD2 (see the file LICENSE)
MaintainerQBayLogic B.V. <devops@qbaylogic.com>
Safe HaskellNone
LanguageHaskell2010

Clash.Explicit.BlockRam.Model

Description

Configurable model for true dual-port block RAM

Synopsis

Documentation

data Conflict Source #

Helper used in getConflict

Constructors

Conflict 

Fields

Instances

Instances details
Show Conflict Source # 
Instance details

Defined in Clash.Explicit.BlockRam.Model

getConflict Source #

Arguments

:: (MaybeX Bool, MaybeX Bool, MaybeX Int)

Port A: enable, write enable, address

-> (MaybeX Bool, MaybeX Bool, MaybeX Int)

Port B: enable, write enable, address

-> Maybe Conflict

Just if there is a (potential) write conflict, otherwise Nothing

Determines whether there was a write-write or read-write conflict. A conflict occurs when two ports tried to (potentially, in case of undefined values) access the same address and one or both tried to write to it. See documentation of Conflict for more information.

cycleOne Source #

Arguments

:: forall nAddrs a writeEnable. (HasCallStack, NFDataX a) 
=> SNat nAddrs 
-> TdpbramModelConfig writeEnable a 
-> a

Previous value

-> Seq a

Memory

-> (MaybeX Bool, MaybeX Int, MaybeX writeEnable, a)

Port: enable, address, write enable, write data

-> (Seq a, a)

Updated memory, output value

Step through a cycle of a TDP block RAM where only one clock is active. Like accessRam, it accounts for XException in all values supplied by the user of the block RAM.

cycleBoth Source #

Arguments

:: forall nAddrs a writeEnable. (NFDataX a, HasCallStack) 
=> SNat nAddrs 
-> TdpbramModelConfig writeEnable a 
-> a

Previous value for port A

-> a

Previous value for port B

-> Seq a

Memory

-> (MaybeX Bool, MaybeX Int, MaybeX writeEnable, a)

Port A: enable, address, write enable, write data

-> (MaybeX Bool, MaybeX Int, MaybeX writeEnable, a)

Port B: enable, address, write enable, write data

-> (Seq a, a, a)

Updated memory, output value A, output value B

Step through a cycle of a TDP block RAM where the clock edges of port A and port B coincided. Like accessRam, it accounts for XException in all values supplied by the user of the block RAM.

accessRam Source #

Arguments

:: forall nAddrs a writeEnable. (NFDataX a, HasCallStack) 
=> SNat nAddrs 
-> (MaybeX writeEnable -> MaybeX Bool)

Determine whether a write enable is active

-> (Int -> MaybeX writeEnable -> a -> Seq a -> Seq a)

Update memory with a defined address

-> MaybeX Int

Address

-> MaybeX writeEnable

Byte enable

-> a

Data to write

-> Seq a

Memory to write to

-> (a, Seq a)

(Read after write value, new memory)

Access a RAM and account for undefined values in the address, write enable, and data to write. Return read after write value.

data TdpbramModelConfig writeEnable a Source #

Constructors

TdpbramModelConfig 

Fields

tdpbramModel Source #

Arguments

:: forall nAddrs domA domB a writeEnable. (HasCallStack, KnownNat nAddrs, KnownDomain domA, KnownDomain domB, NFDataX a) 
=> TdpbramModelConfig writeEnable a 
-> Clock domA 
-> Signal domA Bool

Enable

-> Signal domA (Index nAddrs)

Address

-> Signal domA writeEnable

Write enable

-> Signal domA a

Write data

-> Clock domB 
-> Signal domB Bool

Enable

-> Signal domB (Index nAddrs)

Address

-> Signal domB writeEnable

Write byte enable

-> Signal domB a

Write data

-> (Signal domA a, Signal domB a) 

Haskell model for a true dual-port block RAM which is polymorphic in its write enables