Clash has synchronous Signals in the form of:

Signal (dom :: Domain) a

Where a is the type of the value of the Signal, for example Int or Bool, and dom is the clock- (and reset-) domain to which the memory elements manipulating these Signals belong.

The type-parameter, dom, is of the kind Domain - a simple string. That string refers to a single synthesis domain. A synthesis domain describes the behavior of certain aspects of memory elements in it.

• NB: "Bad things"™ happen when you actually use a clock period of 0, so do not do that!
• NB: You should be judicious using a clock with period of 1 as you can never create a clock that goes any faster!
• NB: For the best compatibility make sure your period is divisible by 2, because some VHDL simulators don't support fractions of picoseconds.
• NB: Whether System has good defaults depends on your target platform. Check out IntelSystem and XilinxSystem too!

Signals have the type role

>>> :i Signal
type role Signal nominal representational
...

as it is safe to coerce the underlying value of a signal, but not safe to coerce a signal between different synthesis domains.

See the module documentation of Clash.Signal for more information about domains.

We either get evidence that this function was instantiated with the same domains, or Nothing.

A KnownDomain constraint indicates that a circuit's behavior depends on some properties of a domain. See DomainConfiguration for more information.

Version of knownDomain that takes a SSymbol. For example:

>>> knownDomainByName (SSymbol @"System")
SDomainConfiguration {sName = SSymbol @"System", sPeriod = SNat @10000, sActiveEdge = SRising, sResetKind = SAsynchronous, sInitBehavior = SDefined, sResetPolarity = SActiveHigh}

Determines clock edge memory elements are sensitive to. Not yet implemented.

Singleton version of ActiveEdge

Singleton version of ResetKind

Determines the value for which a reset line is considered "active"

Singleton version of ResetPolarity

A domain with a name (Domain). Configures the behavior of various aspects of a circuits. See the documentation of this record's field types for more information on the options.

See module documentation of Clash.Explicit.Signal for more information on how to create custom synthesis domains.

Singleton version of DomainConfiguration

Convenience type to help to extract a period from a domain. Example usage:

myFunc :: (KnownDomain dom, DomainPeriod dom ~ 6000) => ...

Convenience type to help to extract the active edge from a domain. Example usage:

myFunc :: (KnownDomain dom, DomainActiveEdge dom ~ 'Rising) => ...

Convenience type to help to extract the reset synchronicity from a domain. Example usage:

myFunc :: (KnownDomain dom, DomainResetKind dom ~ 'Synchronous) => ...

Convenience type to help to extract the initial value behavior from a domain. Example usage:

myFunc :: (KnownDomain dom, DomainInitBehavior dom ~ 'Defined) => ...

Convenience type to help to extract the reset polarity from a domain. Example usage:

myFunc :: (KnownDomain dom, DomainResetPolarity dom ~ 'ActiveHigh) => ...

Helper type family for DomainPeriod

Helper type family for DomainActiveEdge

Helper type family for DomainResetKind

Helper type family for DomainInitBehavior

Helper type family for DomainResetPolarity

Convenience type to constrain a domain to have synchronous resets. Example usage:

myFunc :: HasSynchronousReset dom => ...

Using this type implies KnownDomain.

Click here for usage hints

Convenience type to constrain a domain to have asynchronous resets. Example usage:

myFunc :: HasAsynchronousReset dom => ...

Using this type implies KnownDomain.

Click here for usage hints

Convenience type to constrain a domain to have initial values. Example usage:

myFunc :: HasDefinedInitialValues dom => ...

Using this type implies KnownDomain.

Note that there is no UnknownInitialValues dom as a component that works without initial values will also work if it does have them.

Click here for usage hints

A clock (and reset) dom with clocks running at 100 MHz. Memory elements respond to the rising edge of the clock, and asynchronously to changes in reset signals. It has defined initial values, and active-high resets.

See module documentation of Clash.Explicit.Signal for more information on how to create custom synthesis domains.

A clock (and reset) dom with clocks running at 100 MHz. Memory elements respond to the rising edge of the clock, and synchronously to changes in reset signals. It has defined initial values, and active-high resets.

See module documentation of Clash.Explicit.Signal for more information on how to create custom synthesis domains.

A clock (and reset) dom with clocks running at 100 MHz. Memory elements respond to the rising edge of the clock, and asynchronously to changes in reset signals. It has defined initial values, and active-high resets.

See module documentation of Clash.Explicit.Signal for more information on how to create custom synthesis domains.

Convenience value to allow easy "subclassing" of System domain. Should be used in combination with createDomain. For example, if you just want to change the period but leave all other settings intact use:

createDomain vSystem{vName="System10", vPeriod=10}

Convenience value to allow easy "subclassing" of IntelSystem domain. Should be used in combination with createDomain. For example, if you just want to change the period but leave all other settings intact use:

createDomain vIntelSystem{vName="Intel10", vPeriod=10}

Convenience value to allow easy "subclassing" of XilinxSystem domain. Should be used in combination with createDomain. For example, if you just want to change the period but leave all other settings intact use:

createDomain vXilinxSystem{vName="Xilinx10", vPeriod=10}

Same as SDomainConfiguration but allows for easy updates through record update syntax. Should be used in combination with vDomain and createDomain. Example:

createDomain (knownVDomain @System){vName="System10", vPeriod=10}

This duplicates the settings in the System domain, replaces the name and period, and creates an instance for it. As most users often want to update the system domain, a shortcut is available in the form:

createDomain vSystem{vName="System10", vPeriod=10}

Convert SDomainConfiguration to VDomainConfiguration. Should be used in combination with createDomain only.

Convenience method to express new domains in terms of others.

createDomain (knownVDomain @System){vName="System10", vPeriod=10}

This duplicates the settings in the System domain, replaces the name and period, and creates an instance for it. As most users often want to update the system domain, a shortcut is available in the form:

createDomain vSystem{vName="System10", vPeriod=10}

The function will create two extra identifiers. The first:

type System10 = ..

You can use that as the dom to Clocks/Resets/Enables/Signals. For example: Signal System10 Int. Additionally, it will create a VDomainConfiguration that you can use in later calls to createDomain:

vSystem10 = knownVDomain @System10

It will also make System10 an instance of KnownDomain.

If either identifier is already in scope it will not be generated a second time. Note: This can be useful for example when documenting a new domain:

-- | Here is some documentation for CustomDomain
type CustomDomain = ("CustomDomain" :: Domain)

-- | Here is some documentation for vCustomDomain
createDomain vSystem{vName="CustomDomain"}

A clock signal belonging to a domain named dom.

The negative or inverted phase of a differential clock signal. HDL generation will treat it the same as Clock, except that no create_clock command is issued in the SDC file for ClockN. Used in DiffClock.

A differential clock signal belonging to a domain named dom. The clock input of a design with such an input has two ports which are in antiphase. The first input is the positive phase, the second the negative phase. When using makeTopEntity, the names of the inputs will end in _p and _n respectively.

To create a differential clock in a test bench, you can use clockToDiffClock.

Calculate the period in ps, given a frequency in Hz

I.e., to calculate the clock period for a circuit to run at 240 MHz we get

>>> hzToPeriod 240e6
4166

If the value hzToPeriod is applied to is not of the type Ratio Natural, you can use hzToPeriod (realToFrac f). Note that if f is negative, realToFrac will give an Underflow :: ArithException without a call stack, making debugging cumbersome.

Before Clash 1.8, this function always returned a Natural. To get the old behavior of this function, use a type application:

>>> hzToPeriod @Natural 240e6
4166

• NB: This function is not synthesizable
• NB: This function is lossy. I.e., periodToHz . hzToPeriod /= id.

Calculate the frequency in Hz, given the period in ps

I.e., to calculate the clock frequency of a clock with a period of 5000 ps:

>>> periodToHz 5000
2.0e8

Note that if p in periodToHz (fromIntegral p) is negative, fromIntegral will give an Underflow :: ArithException without a call stack, making debugging cumbersome.

Before Clash 1.8, this function always returned a Ratio Natural. To get the old behavior of this function, use a type application:

>>> periodToHz @(Ratio Natural) 5000
200000000 % 1

NB: This function is not synthesizable

Given two clocks, produce a list of clock ticks indicating which clock (or both) ticked. Can be used in components handling multiple clocks, such as unsafeSynchronizer or dual clock FIFOs.

If your primitive does not care about coincided clock edges, it should - by convention - replace it by ClockB:ClockA:.

Given two clock periods, produce a list of clock ticks indicating which clock (or both) ticked. Can be used in components handling multiple clocks, such as unsafeSynchronizer or dual clock FIFOs.

If your primitive does not care about coincided clock edges, it should - by convention - replace it by ClockB:ClockA:.

A signal of booleans, indicating whether a component is enabled. No special meaning is implied, it's up to the component itself to decide how to respond to its enable line. It is used throughout Clash as a global enable signal.

Convert a signal of bools to an Enable construct

Convert Enable construct to its underlying representation: a signal of bools.

Enable generator for some domain. Is simply always True.

A reset signal belonging to a domain called dom.

The underlying representation of resets is Bool.

unsafeToReset is unsafe. For asynchronous resets it is unsafe because it can introduce combinatorial loops. In case of synchronous resets it can lead to meta-stability issues in the presence of asynchronous resets.

NB: You probably want to use unsafeFromActiveLow or unsafeFromActiveHigh.

unsafeFromReset is unsafe because it can introduce:

• meta-stability

For asynchronous resets it is unsafe because it can cause combinatorial loops. In case of synchronous resets it can lead to meta-stability in the presence of asynchronous resets.

NB: You probably want to use unsafeToActiveLow or unsafeToActiveHigh.

Convert a reset to an active high reset. Has no effect if reset is already an active high reset. Is unsafe because it can introduce:

• meta-stability

For asynchronous resets it is unsafe because it can cause combinatorial loops. In case of synchronous resets it can lead to meta-stability in the presence of asynchronous resets.

Convert a reset to an active low reset. Has no effect if reset is already an active low reset. It is unsafe because it can introduce:

• meta-stability

For asynchronous resets it is unsafe because it can cause combinatorial loops. In case of synchronous resets it can lead to meta-stability in the presence of asynchronous resets.

Interpret a signal of bools as an active high reset and convert it to a reset signal corresponding to the domain's setting.

For asynchronous resets it is unsafe because it can cause combinatorial loops. In case of synchronous resets it can lead to meta-stability in the presence of asynchronous resets.

Interpret a signal of bools as an active low reset and convert it to a reset signal corresponding to the domain's setting.

For asynchronous resets it is unsafe because it can cause combinatorial loops. In case of synchronous resets it can lead to meta-stability in the presence of asynchronous resets.

Invert reset signal

A register with a power up and reset value. Power up values are not supported on all platforms, please consult the manual of your target platform and check the notes below.

Xilinx: power up values and reset values MUST be the same. If they are not, the Xilinx tooling will ignore the reset value and use the power up value instead. Source: MIA

Intel: power up values and reset values MUST be the same. If they are not, the Intel tooling will ignore the power up value and use the reset value instead. Source: https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd01072011_91.html

Version of register# that simulates a register on an asynchronous domain. Is synthesizable.

Version of register# that simulates a register on a synchronous domain. Not synthesizable.

Acts like id if given domain allows powerup values, but returns a value constructed with deepErrorX otherwise.

The above type is a generalization for:

mux :: Signal Bool -> Signal a -> Signal a -> Signal a

A multiplexer. Given "mux b t f", output t when b is True, and f when b is False.

Clock generator for simulations. Do not use this clock generator for the testBench function, use tbClockGen instead.

To be used like:

clkSystem = clockGen @System

See DomainConfiguration for more information on how to use synthesis domains.

Clock generator to be used in the testBench function.

To be used like:

clkSystem en = tbClockGen @System en

Example

module Example where

import Clash.Explicit.Prelude
import Clash.Explicit.Testbench

-- Fast domain: twice as fast as "Slow"
createDomain vSystem{vName="Fast", vPeriod=10}

-- Slow domain: twice as slow as "Fast"
createDomain vSystem{vName="Slow", vPeriod=20}

topEntity
  :: Clock "Fast"
  -> Reset "Fast"
  -> Enable "Fast"
  -> Clock "Slow"
  -> Signal "Fast" (Unsigned 8)
  -> Signal "Slow" (Unsigned 8, Unsigned 8)
topEntity clk1 rst1 en1 clk2 i =
  let h = register clk1 rst1 en1 0 (register clk1 rst1 en1 0 i)
      l = register clk1 rst1 en1 0 i
  in  unsafeSynchronizer clk1 clk2 (bundle (h, l))

testBench
  :: Signal "Slow" Bool
testBench = done
  where
    testInput      = stimuliGenerator clkA1 rstA1 $(listToVecTH [1::Unsigned 8,2,3,4,5,6,7,8])
    expectedOutput = outputVerifier   clkB2 rstB2 $(listToVecTH [(0,0) :: (Unsigned 8, Unsigned 8),(1,2),(3,4),(5,6),(7,8)])
    done           = expectedOutput (topEntity clkA1 rstA1 enableGen clkB2 testInput)
    notDone        = not <$> done
    clkA1          = tbClockGen @"Fast" (unsafeSynchronizer clkB2 clkA1 notDone)
    clkB2          = tbClockGen @"Slow" notDone
    rstA1          = resetGen @"Fast"
    rstB2          = resetGen @"Slow"

Femtoseconds expressed as an Int64. Is a newtype to prevent accidental mixups with picoseconds - the unit used in DomainConfiguration.

Calculate the frequency in Hz, given the period in fs

I.e., to calculate the clock frequency of a clock with a period of 5000 fs:

>>> fsToHz (Femtoseconds 5000)
2.0e11

NB: This function is not synthesizable

Calculate the period in fs, given a frequency in Hz

I.e., to calculate the clock period for a circuit to run at 240 MHz we get

>>> hzToFs 240e6
Femtoseconds 4166666

If the value hzToFs is applied to is not of the type Ratio Natural, you can use hzToFs (realToFrac f). Note that if f is negative, realToFrac will give an Underflow :: ArithException without a call stack, making debugging cumbersome.

• NB: This function is not synthesizable
• NB: This function is lossy. I.e., fsToHz . hzToFs /= id.

Strip newtype wrapper Femtoseconds

Map Int64 fields in Femtoseconds

Clock generator with dynamic clock periods for simulations. This is an experimental feature and hence not part of the public API. Like tbClockGen

To be used like:

clkSystem = dynamicClockGen @System

See DomainConfiguration for more information on how to use synthesis domains.

Clock generator with dynamic clock periods for simulations. This is an experimental feature and hence not part of the public API.

To be used like:

clkSystem = dynamicClockGen @System

See DomainConfiguration for more information on how to use synthesis domains.

Reset generator for simulation purposes. Asserts the reset for a single cycle.

To be used like:

rstSystem = resetGen @System

See tbClockGen for example usage.

NB: While this can be used in the testBench function, it cannot be synthesized to hardware.

Reset generator for simulation purposes. Asserts the reset for the first n cycles.

To be used like:

rstSystem5 = resetGen @System d5

Example usage:

>>> sampleN 7 (unsafeToActiveHigh (resetGenN @System d3))
[True,True,True,False,False,False,False]

NB: While this can be used in the testBench function, it cannot be synthesized to hardware.

The above type is a generalization for:

(.&&.) :: Signal Bool -> Signal Bool -> Signal Bool

It is a version of (&&) that returns a Signal of Bool

The above type is a generalization for:

(.||.) :: Signal Bool -> Signal Bool -> Signal Bool

It is a version of (||) that returns a Signal of Bool

Simulate a (Signal a -> Signal b) function given a list of samples of type a

>>> simulate (register systemClockGen resetGen enableGen 8) [1, 1, 2, 3]
[8,8,1,2,3...
...

NB: This function is not synthesizable