Copyright | © 2015-2016 Christiaan Baaij 2017 Google Inc. 2019 Myrtle Software Ltd |
---|---|
License | Creative Commons 4.0 (CC BY 4.0) (https://creativecommons.org/licenses/by/4.0/) |
Safe Haskell | None |
Language | Haskell2010 |
Documentation
upCounterLd :: HiddenClockResetEnable dom => Signal dom (Bool, Bool, Unsigned 8) -> Signal dom (Unsigned 8) Source #
upDownCounter :: HiddenClockResetEnable dom => Signal dom Bool -> Signal dom (Unsigned 8) Source #
grayCounter :: HiddenClockResetEnable dom => Signal dom Bool -> Signal dom (BitVector 8) Source #
oneHotCounter :: HiddenClockResetEnable dom => Signal dom Bool -> Signal dom (BitVector 8) Source #
crc :: HiddenClockResetEnable dom => Signal dom Bool -> Signal dom Bool -> Signal dom Bit -> Signal dom (BitVector 16) Source #
Instances
Instances
Generic TxReg Source # | |
NFDataX TxReg Source # | |
Defined in Clash.Examples.Internal | |
type Rep TxReg Source # | |
Defined in Clash.Examples.Internal type Rep TxReg = D1 ('MetaData "TxReg" "Clash.Examples.Internal" "clash-prelude-1.7.0-inplace" 'False) (C1 ('MetaCons "TxReg" 'PrefixI 'True) ((S1 ('MetaSel ('Just "_tx_reg") 'NoSourceUnpackedness 'NoSourceStrictness 'DecidedLazy) (Rec0 (BitVector 8)) :*: S1 ('MetaSel ('Just "_tx_empty") 'NoSourceUnpackedness 'NoSourceStrictness 'DecidedLazy) (Rec0 Bool)) :*: (S1 ('MetaSel ('Just "_tx_over_run") 'NoSourceUnpackedness 'NoSourceStrictness 'DecidedLazy) (Rec0 Bool) :*: (S1 ('MetaSel ('Just "_tx_out") 'NoSourceUnpackedness 'NoSourceStrictness 'DecidedLazy) (Rec0 Bit) :*: S1 ('MetaSel ('Just "_tx_cnt") 'NoSourceUnpackedness 'NoSourceStrictness 'DecidedLazy) (Rec0 (Unsigned 4)))))) |
uart :: forall (dom1 :: Symbol) (dom2 :: Symbol). (KnownDomain dom1, KnownDomain dom2, IP (AppendSymbol dom1 "_clk") (Clock dom1), IP (AppendSymbol dom1 "_rst") (Reset dom1), IP (AppendSymbol dom1 "_en") (Enable dom1), IP (AppendSymbol dom2 "_clk") (Clock dom2), IP (AppendSymbol dom2 "_rst") (Reset dom2), IP (AppendSymbol dom2 "_en") (Enable dom2)) => Signal dom1 Bool -> Signal dom1 (BitVector 8) -> Signal dom1 Bool -> Signal dom2 Bit -> Signal dom2 Bool -> Signal dom2 Bool -> (Signal dom1 Bit, Signal dom1 Bool, Signal dom2 (BitVector 8), Signal dom2 Bool) Source #