Documentation

A clock source that corresponds to the Intel/Quartus "ALTPLL" component (Arria GX, Arria II, Stratix IV, Stratix III, Stratix II, Stratix, Cyclone 10 LP, Cyclone IV, Cyclone III, Cyclone II, Cyclone) with settings to provide a stable Clock from a single free-running input

Only works when configured with:

• 1 reference clock
• 1 output clock
• a reset input port
• a locked output port

The PLL lock output is asserted when the clock is stable, and is usually connected to reset circuitry to keep the circuit in reset while the clock is still stabilizing.

See also the ALTPLL (Phase-Locked Loop) IP Core User Guide

Example

Using a PLL

When the oscillator connected to the FPGA runs at 50 MHz and the external reset signal is active low, this will generate a 100 MHz clock for the System domain:

createDomain vSystem{vName="DomInput", vPeriod=20000}

topEntity
  :: Clock DomInput
  -> Signal DomInput Bool
  -> [...]
topEntity clkInp rstInp = [...]
 where
  (clk, pllStable) =
    altpll @System (SSymbol @"altpll50to100") clkInp
           (unsafeFromLowPolarity rstInp)
  rst = resetSynchronizer clk (unsafeFromLowPolarity pllStable)

resetSynchronizer will keep the reset asserted when pllStable is False, hence the use of unsafeFromLowPolarity pllStable. Your circuit will have signals of type Signal System and all the clocks and resets of your components will be the clk and rst signals generated here (modulo local resets, which will be based on rst or never asserted at all if the component doesn't need a reset).

Specifying the output frequency

If you don't have a top-level type signature specifying the output clock domain, you can use type applications to specify it, e.g.:

createDomain vSystem{vName="Dom100MHz", vPeriod=10000}

-- outputs a clock running at 100 MHz
(clk100, pllLocked) = altpll @Dom100MHz (SSymbol @"altpll50to100") clk50 rst50

A clock source that corresponds to the Intel/Quartus "Altera PLL" component (Arria V, Stratix V, Cyclone V) with settings to provide a stable Clock from a single free-running input

Only works when configured with:

• 1 reference clock
• 1-16 output clocks
• a reset input port
• a locked output port

The PLL lock output is asserted when the clocks are stable, and is usually connected to reset circuitry to keep the circuit in reset while the clocks are still stabilizing.

See also the Altera Phase-Locked Loop (Altera PLL) IP Core User Guide

Specifying outputs

The number of output clocks depends on this function's inferred result type. An instance with a single output clock can be instantiated using:

createDomain vSystem{vName="Dom100MHz", vPeriod=10000}

(clk100 :: Clock Dom100MHz, pllLocked) =
  alteraPll (SSymbol @"alterapll50to100") clk50 rst50

An instance with two clocks can be instantiated using

createDomain vSystem{vName="Dom100MHz", vPeriod=10000}
createDomain vSystem{vName="Dom150MHz", vPeriod=hzToPeriod 150e6}

(clk100 :: Clock Dom100MHz, clk150 :: Clock Dom150MHz, pllLocked) =
  alteraPll (SSymbol @"alterapllmulti") clk50 rst50

and so on up to 16 clocks.

If you don't have a top-level type signature specifying the output clock domains, you can specify them using a pattern type signature, as shown here.

Example

When the oscillator connected to the FPGA runs at 50 MHz and the external reset signal is active low, this will generate a 100 MHz clock for the System domain:

createDomain vSystem{vName="DomInput", vPeriod=20000}

topEntity
  :: Clock DomInput
  -> Signal DomInput Bool
  -> [...]
topEntity clkInp rstInp = [...]
 where
  (clk :: Clock System, pllStable :: Signal System Bool)
    alteraPll (SSymbol @"alterapll50to100") clkInp
              (unsafeFromLowPolarity rstInp)
  rst = resetSynchronizer clk (unsafeFromLowPolarity pllStable)

resetSynchronizer will keep the reset asserted when pllStable is False, hence the use of unsafeFromLowPolarity pllStable. Your circuit will have signals of type Signal System and all the clocks and resets of your components will be the clk and rst signals generated here (modulo local resets, which will be based on rst or never asserted at all if the component doesn't need a reset).