Copyright | (C) 2015-2016 University of Twente 2017-2019 Myrtle Software Ltd 2017 Google Inc. 2021-2022 QBayLogic B.V. |
---|---|
License | BSD2 (see the file LICENSE) |
Maintainer | QBayLogic B.V. <devops@qbaylogic.com> |
Safe Haskell | Safe |
Language | Haskell2010 |
Extensions |
|
RAM primitives with a combinational read port.
Synopsis
- asyncRam :: (Enum addr, HiddenClock dom, HiddenEnable dom, HasCallStack) => SNat n -> Signal dom addr -> Signal dom (Maybe (addr, a)) -> Signal dom a
- asyncRamPow2 :: (KnownNat n, HiddenClock dom, HiddenEnable dom, HasCallStack) => Signal dom (Unsigned n) -> Signal dom (Maybe (Unsigned n, a)) -> Signal dom a
RAM synchronized to an arbitrary clock
:: (Enum addr, HiddenClock dom, HiddenEnable dom, HasCallStack) | |
=> SNat n | Size |
-> Signal dom addr | Read address |
-> Signal dom (Maybe (addr, a)) | (write address |
-> Signal dom a | Value of the |
Create a RAM with space for n
elements.
- NB: Initial content of the RAM is undefined, reading it will throw an
XException
Additional helpful information:
- See Clash.Prelude.BlockRam for more information on how to use a RAM.
:: (KnownNat n, HiddenClock dom, HiddenEnable dom, HasCallStack) | |
=> Signal dom (Unsigned n) | Read address |
-> Signal dom (Maybe (Unsigned n, a)) | (write address |
-> Signal dom a | Value of the |
Create a RAM with space for 2^n
elements
- NB: Initial content of the RAM is undefined, reading it will throw an
XException
Additional helpful information:
- See Clash.Prelude.BlockRam for more information on how to use a RAM.