| Copyright | (C) 2015-2016 University of Twente 2017 Google Inc. |
|---|---|
| License | BSD2 (see the file LICENSE) |
| Maintainer | Christiaan Baaij <christiaan.baaij@gmail.com> |
| Safe Haskell | Unsafe |
| Language | Haskell2010 |
| Extensions |
|
Clash.Explicit.ROM.File
Description
Initialising a ROM with a data file
ROMs initialised with a data file. The BNF grammar for this data file is simple:
FILE = LINE+
LINE = BIT+
BIT = '0'
| '1'
Consecutive LINEs correspond to consecutive memory addresses starting at 0.
For example, a data file memory.bin containing the 9-bit unsigned number
7 to 13 looks like:
000000111 000001000 000001001 000001010 000001011 000001100 000001101
We can instantiate a synchronous ROM using the content of the above file like so:
f :: Clock domain gated -> Signal domain (Unsigned 3) -> Signal domain (Unsigned 9) f clk rd =unpack<$>romFileclk d7 "memory.bin" rd
And see that it works as expected:
>>> import qualified Data.List as L >>> L.tail $ sampleN 4 $ f systemClockGen (fromList [3..5]) [10,11,12]
However, we can also interpret the same data as a tuple of a 6-bit unsigned number, and a 3-bit signed number:
g :: Clock domain Source -> Signal domain (Unsigned 3) -> Signal domain (Unsigned 6,Signed 3) g clk rd =unpack<$>romFileclk d7 "memory.bin" rd
And then we would see:
>>> import qualified Data.List as L >>> L.tail $ sampleN 4 $ g systemClockGen (fromList [3..5]) [(1,2),(1,3)(1,-4)]
Synopsis
- romFile :: (KnownNat m, Enum addr) => Clock domain gated -> SNat n -> FilePath -> Signal domain addr -> Signal domain (BitVector m)
- romFilePow2 :: forall domain gated n m. (KnownNat m, KnownNat n) => Clock domain gated -> FilePath -> Signal domain (Unsigned n) -> Signal domain (BitVector m)
- romFile# :: KnownNat m => Clock domain gated -> SNat n -> FilePath -> Signal domain Int -> Signal domain (BitVector m)
Synchronous ROM synchronised to an arbitrary clock
Arguments
| :: (KnownNat m, Enum addr) | |
| => Clock domain gated |
|
| -> SNat n | Size of the ROM |
| -> FilePath | File describing the content of the ROM |
| -> Signal domain addr | Read address |
| -> Signal domain (BitVector m) | The value of the ROM at address |
A ROM with a synchronous read port, with space for n elements
- NB: Read value is delayed by 1 cycle
- NB: Initial output value is
undefined NB: This function might not work for specific combinations of code-generation backends and hardware targets. Please check the support table below:
| VHDL | Verilog | SystemVerilog | ===============+==========+==========+===============+ Altera/Quartus | Broken | Works | Works | Xilinx/ISE | Works | Works | Works | ASIC | Untested | Untested | Untested | ===============+==========+==========+===============+
Additional helpful information:
- See Clash.Explicit.ROM.File for more information on how to instantiate a ROM with the contents of a data file.
- See Clash.Sized.Fixed for ideas on how to create your own data files.
Arguments
| :: (KnownNat m, KnownNat n) | |
| => Clock domain gated |
|
| -> FilePath | File describing the content of the ROM |
| -> Signal domain (Unsigned n) | Read address |
| -> Signal domain (BitVector m) | The value of the ROM at address |
A ROM with a synchronous read port, with space for 2^n elements
- NB: Read value is delayed by 1 cycle
- NB: Initial output value is
undefined NB: This function might not work for specific combinations of code-generation backends and hardware targets. Please check the support table below:
| VHDL | Verilog | SystemVerilog | ===============+==========+==========+===============+ Altera/Quartus | Broken | Works | Works | Xilinx/ISE | Works | Works | Works | ASIC | Untested | Untested | Untested | ===============+==========+==========+===============+
Additional helpful information:
- See Clash.Explicit.ROM.File for more information on how to instantiate a ROM with the contents of a data file.
- See Clash.Sized.Fixed for ideas on how to create your own data files.