Copyright | (C) 2015-2016 University of Twente |
---|---|
License | BSD2 (see the file LICENSE) |
Maintainer | Christiaan Baaij <christiaan.baaij@gmail.com> |
Safe Haskell | Trustworthy |
Language | Haskell2010 |
Extensions |
|
Synchronizer circuits for safe clock domain crossings
Bit-synchronizers
dualFlipFlopSynchronizer Source #
:: SClock clk1 |
|
-> SClock clk2 |
|
-> a | Initial value of the two synchronisation registers |
-> Signal' clk1 a | Incoming data |
-> Signal' clk2 a | Outgoing, synchronised, data |
Synchroniser based on two sequentially connected flip-flops.
- NB: This synchroniser can be used for bit-synchronization.
NB: Although this synchroniser does reduce metastability, it does not guarantee the proper synchronisation of a whole word. For example, given that the output is sampled twice as fast as the input is running, and we have two samples in the input stream that look like:
[0111,1000]
But the circuit driving the input stream has a longer propagation delay on msb compared to the lsbs. What can happen is an output stream that looks like this:
[0111,0111,0000,1000]
Where the level-change of the msb was not captured, but the level change of the lsbs were.
If you want to have safe word-synchronisation use
asyncFIFOSynchronizer
.
Word-synchronizers
asyncFIFOSynchronizer Source #
:: 2 <= addrSize | |
=> SNat addrSize | Size of the internally used addresses, the
FIFO contains |
-> SClock wclk |
|
-> SClock rclk |
|
-> Signal' rclk Bool | Read request |
-> Signal' wclk (Maybe a) | Element to insert |
-> (Signal' rclk a, Signal' rclk Bool, Signal' wclk Bool) | (Oldest element in the FIFO, |
Synchroniser implemented as a FIFO around an asynchronous RAM. Based on the design described in CLaSH.Tutorial, which is itself based on the design described in http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO1.pdf.
NB: This synchroniser can be used for word-synchronization.