Documentation

Fields

• !Identifier

  Signal to assign

• !Usage

  How the signal is assigned

• !Expr

  Assigned expression

Fields

• !Identifier

  Signal to assign

• !HWType

  Type of the result/alternatives

• !Expr

  Scrutinized expression

• !HWType

  Type of the scrutinee

• [(Maybe Literal, Expr)]

  List of: (Maybe expression scrutinized expression is compared with,RHS of alternative)

Fields

• EntityOrComponent

  Whether it's an entity or a component

• (Maybe Text)

  Library instance is defined in

• [Attr Text]

  Attributes to add to the generated code

• !Identifier

  The component's (or entity's) name

• !Identifier

  Instance label

• [(Expr, HWType, Expr)]

  List of parameters for this component (param name, param type, param value)

• PortMap
   

Fields

• !Text

  Primitive name

• [BlackBoxTemplate]

  VHDL only: add library declarations

• [BlackBoxTemplate]

  VHDL only: add use declarations

• [((Text, Text), BlackBox)]

  Intel Quartus only: create a .qsys file from given template

• !BlackBox

  Template tokens

• BlackBoxContext

  Context in which tokens should be rendered

Fields

• (Maybe Comment)

  Note; will be inserted as a comment in target hdl

• !Identifier

  Name of signal

• HWType

  Type of signal

• (Maybe Expr)

  Initial value ^ Signal declaration

Fields

• !Text

  condition text, for example FORMAL

• [Declaration]
   

Fields

• runNetlist :: StateT NetlistState (ReaderT NetlistEnv IO) a
   

Fields

• topId :: Id

  Id of top entity

• topAnnotation :: Maybe TopEntity

  (Maybe) a topentity annotation

• topIsTestBench :: Bool

  Whether this entity is a test bench

Fields

• !Text

  Primitive name

• [BlackBoxTemplate]

  VHDL only: add library declarations

• [BlackBoxTemplate]

  VHDL only: add use declarations:

• [((Text, Text), BlackBox)]

  Intel/Quartus only: create a .qsys file from given template.

• !BlackBox

  Template tokens

• !BlackBoxContext

  Context in which tokens should be rendered

• !Bool

  Wrap in parentheses?

Fields

• (Maybe Identifier)

  Type prefix

• HWType

  Type to convert _from_

• Expr

  Expression to convert to BitVector

Fields

• (Maybe Identifier)

  Type prefix

• HWType

  Type to convert _to_

• Expr

  BitVector to convert

Fields

• componentName :: !Identifier

  Name of the component

• inputs :: [(Identifier, HWType)]

  Input ports

• outputs :: [(Usage, (Identifier, HWType), Maybe Expr)]

  Output ports

• declarations :: [Declaration]

  Internal declarations

Fields

• !Identifier

  Signal to assign

• !Usage

  How the signal is assigned

• !Expr

  Assigned expression

Fields

• !Identifier

  Signal to assign

• !HWType

  Type of the result/alternatives

• !Expr

  Scrutinized expression

• !HWType

  Type of the scrutinee

• [(Maybe Literal, Expr)]

  List of: (Maybe expression scrutinized expression is compared with,RHS of alternative)

Fields

• EntityOrComponent

  Whether it's an entity or a component

• (Maybe Text)

  Library instance is defined in

• [Attr Text]

  Attributes to add to the generated code

• !Identifier

  The component's (or entity's) name

• !Identifier

  Instance label

• [(Expr, HWType, Expr)]

  List of parameters for this component (param name, param type, param value)

• PortMap
   

Fields

• !Text

  Primitive name

• [BlackBoxTemplate]

  VHDL only: add library declarations

• [BlackBoxTemplate]

  VHDL only: add use declarations

• [((Text, Text), BlackBox)]

  Intel Quartus only: create a .qsys file from given template

• !BlackBox

  Template tokens

• BlackBoxContext

  Context in which tokens should be rendered

Fields

• (Maybe Comment)

  Note; will be inserted as a comment in target hdl

• !Identifier

  Name of signal

• HWType

  Type of signal

• (Maybe Expr)

  Initial value ^ Signal declaration

Fields

• !Text

  condition text, for example FORMAL

• [Declaration]
   

Fields

• is_allowEscaped :: !Bool

  Allow escaped ids? If set to False, "make" will always behave like "makeBasic".

• is_lowerCaseBasicIds :: !PreserveCase

  Force all generated basic identifiers to lowercase.

• is_hdl :: !HDL

  HDL to generate fresh identifiers for

• is_freshCache :: !FreshCache

  Maps an i_baseNameCaseFold to a map mapping the number of extensions (in i_extensionsRev) to the maximum word at that basename/level. For example, if a set would contain the identifiers:

  foo, foo_1, foo_2, bar_5, bar_7_8

  the map would look like:

  (foo, [(0, 0), (1, 2)

  ), (bar, [(1, 5), (2, 8)])]

  This mapping makes sure we can quickly generate fresh identifiers. For example, generating a new id for "foo_1" would be a matter of looking up the base name in this map, concluding that the maximum identifier with this basename and this number of extensions is "foo_2", subsequently generating "foo_3".

  Note that an identifier with no extensions is also stored in this map for practical purposes, but the maximum ext is invalid.

• is_store :: !(HashSet Identifier)

  Identifier store

Fields

• !Text

  An identifier exactly as given by the user

• (Maybe Identifier)

  Parsed version of raw identifier. Will not be populated if this identifier was created with an unsafe function.

• !CallStack

  Stores where this identifier was generated. Tracking is only enabled is debugIsOn, otherwise this field will be populated by an empty callstack.

Fields

• i_baseName :: !Text

  Base name of identifier. make makes sure this field:

  • does not end in _num where num is a digit.
  • is solely made up of printable ASCII characters
  • has no leading or trailing whitespace
• i_baseNameCaseFold :: !Text

  Same as i_baseName, but can be used for equality testing that doesn't depend on capitalization.

• i_extensionsRev :: [Word]

  Extensions applied to base identifier. E.g., an identifier with a base name of foo and an extension of [6, 5] would render as foo_5_6. Note that extensions are stored in reverse order for easier manipulation.

• i_idType :: !IdentifierType

  See IdentifierType.

• i_hdl :: !HDL

  HDL this identifier is generated for.

• i_provenance :: !CallStack

  Stores where this identifier was generated. Tracking is only enabled is debugIsOn, otherwise this field will be populated by an empty callstack.

Fields

• :: [Int]

  Used arguments

• -> (BlackBoxContext -> Bool)

  Validation function. Should return False if function can't render given a certain context.

• -> (forall s. Backend s => BlackBoxContext -> State s Doc)

  Render function

• -> TemplateFunction
   

Fields

• bbName :: Text

  Blackbox function name (for error reporting)

• bbResults :: [(Expr, HWType)]

  Result names and types. Will typically be a list with a single item. Multiple result targets will be used for "multi result primitives". See setupMultiResultPrim.

• bbInputs :: [(Expr, HWType, Bool)]

  Argument names, types, and whether it is a literal

• bbFunctions :: IntMap [(Either BlackBox (Identifier, [Declaration]), Usage, [BlackBoxTemplate], [BlackBoxTemplate], [((Text, Text), BlackBox)], BlackBoxContext)]

  Function arguments (subset of inputs):

  • ( Blackbox Template , Whether the result should be reg or a wire (Verilog only) , Partial Blackbox Context )
• bbQsysIncName :: [IdentifierText]
   
• bbLevel :: Int

  The scoping level this context is associated with, ensures that ~ARGN[k][n] holes are only filled with values from this context if k is equal to the scoping level of this context.

• bbCompName :: Identifier

  The component the BlackBox is instantiated in

• bbCtxName :: Maybe IdentifierText

  The "context name", name set by setName, defaults to the name of the closest binder

Fields

• ActiveEdge

  Edge of the clock the statement should be executed

• Expr

  Clock expression

• [Seq]

  Statements to be executed on the active clock edge | Statements running at simulator start

Fields

• !Expr

  Scrutinized expresson

• !HWType

  Type of the scrutinized expression

• [(Maybe Literal, [Seq])]

  List of: (Maybe match, RHS of Alternative)

Fields

• componentPrefixTop :: Maybe Text

  Prefix for top-level components

• componentPrefixOther :: Maybe Text

  Prefix for all other components

Fields

• _bindings :: BindingMap

  Global binders

• _components :: ComponentMap

  Cached components. Is an insertion ordered map to preserve a topologically sorted component list for the manifest file.

• _typeTranslator :: CustomReprs -> TyConMap -> Type -> State HWMap (Maybe (Either String FilteredHWType))

  Hardcoded Type -> HWType translator

• _curCompNm :: !(Identifier, SrcSpan)
   
• _seenIds :: IdentifierSet

  All names currently in scope.

• _seenComps :: IdentifierSet

  Components (to be) generated during this netlist run. This is always a subset of seenIds. Reason d'etre: we currently generate components in a top down manner. E.g. given:

  • A
  • - B
  • - C

  we would generate component A first. Before trying to generate B and C. A might introduce a number of signal declarations. The names of these signals can't clash with the name of component B, hence we need to pick a name for B unique w.r.t. all these signal names. If we would postpone generating a unqiue name for B til _after_ generating all the signal names, the signal names would get all the "nice" names. E.g., a signal would be called "foo", thereby forcing the component B to be called "foo_1". Ideally, we'd use the "nice" names for components, and the "ugly" names for signals. To achieve this, we generate all the component names up front and subsequently store them in _seenComps.

• _seenPrimitives :: Set Text

  Keeps track of invocations of ´mkPrimitive´. It is currently used to filter duplicate warning invocations for dubious blackbox instantiations, see GitHub pull request #286.

• _componentNames :: VarEnv Identifier

  Names of components (to be) generated during this netlist run. Includes top entity names.

• _topEntityAnns :: VarEnv TopEntityT
   
• _hdlDir :: FilePath
   
• _curBBlvl :: Int

  The current scoping level assigned to black box contexts

• _isTestBench :: Bool

  Whether we're compiling a testbench (suppresses some warnings)

• _backEndITE :: Bool

  Whether the backend supports ifThenElse expressions

• _backend :: SomeBackend

  The current HDL backend

• _htyCache :: HWMap
   
• _usages :: UsageMap

  The current way signals are assigned in netlist. This is used to determine how signals are rendered in HDL (i.e. wire/reg in Verilog, or signal/variable in VHDL).