Options for blackBoxHaskell function. Use def from package 'data-default' for a set of default options.

Create a blackBoxHaskell primitive. To be used as part of an annotation:

{-# ANN myFunction (blackBoxHaskell 'myFunction 'myBBF def{bo_ignoredArguments=[1,2]}) #-}

[1,2] would mean this blackbox ignores its second and third argument.

The state of a block. Contains a list of declarations and a the backend state.

A typed expression.

Add a declaration to the state.

Assign an expression to an identifier, returns the new typed identifier expression.

This creates a component declaration (for VHDL) given in and out port names, updating the 'BlockState backend' stored in the State monad.

A typical result is that a

component fifo port
   ( rst : in std_logic
   ...
   ; full : out std_logic
   ; empty : out std_logic );
 end component;

declaration would be added in the appropriate place.

Run a block declaration.

Run a block declaration. Assign the result of the block builder to the result variable in the given blackbox context.

Declare a new signal with the given name and type.

Declare n new signals with the given type and based on the given name

Instantiate a component/entity in a block state

Instantiate/call a higher-order function.

Wires the two given TExprs together using a newly declared signal with (exactly) the given name sigNm. The new signal has an annotated type, using the given attributes.

Construct a fully defined BitVector literal

A literal that can be used for hdl attributes. It has a Num and IsString instances for convenience.

The high literal bit.

The low literal bit.

Construct a product type given its type and fields

Create an n-tuple of TExpr

Create a vector of TExprs

The TExp inputs from a blackbox context.

The TExp result of a blackbox context.

Try to get the literal string value of an expression.

Try to get the literal bool value of an expression.

Try to get a Vector of expressions.

Try to get the literal nat value of an expression.

Extract the fields of a product type and return expressions to them. These new expressions are given unique names and get declared in the block scope.

Extract the elements of a tuple expression and return expressions to them. These new expressions are given unique names and get declared in the block scope.

Extract the elements of a vector expression and return expressions to them. If given expression is not an identifier, an intermediate variable will be used to assign the given expression to which is subsequently indexed.

Deconstruct a Maybe into its constructor Bit and contents of its Just field. Note that the contents might be undefined, if the constructor bit is set to Nothing.

Convert an expression from one type to another. Errors if result type and given expression are sized differently.

Convert an expression to a BitVector

Convert an expression to a BitVector and add the given HDL attributes

Convert an expression from a BitVector into some type. If the expression is Annotated, only convert the expression within.

Convert an enable to a bit.

Convert a bool to a bit.

Use to create an output Bool from a Bit. The expression given must be the identifier of the bool you wish to get assigned. Returns a reference to a declared Bit that should get assigned by something (usually the output port of an entity).

Used to create an output Bool from a BitVector of given size. Works in a similar way to boolFromBit above.

TODO: Implement for (System)Verilog

Used to create an output Unsigned from a BitVector of given size. Works in a similar way to boolFromBit above.

Used to create an output Bool from a number of Bits, using conjunction. Similarly to untuple, it returns a list of references to declared values (the inputs to the function) which should get assigned by something---usually output ports of an entity.

TODO: Implement for (System)Verilog

Massage a reset to work as active-high reset.

Massage a reset to work as active-low reset.

And together (&&) two expressions, assigning it to a new identifier.

Negate (not) an expression, assigning it to a new identifier.

Creates a BV that produces the following vhdl:

   (0 to n => ARG)

TODO: Implement for (System)Verilog

Creates a BV that produces the following vhdl:

   std_logic_vector(resize(ARG, Size))

TODO: Implement for (System)Verilog

Allows assignment of a port to be "open"

Convert a LitHDL to a TExpr

N.B.: Clash 1.8 changed instDecl's type signature. Where it would previously accept LitHDL in its generics/parameters argument, it now accepts a TExpr. This function is mostly there to ease this transition.

Get an identifier to an expression, creating a new assignment if necessary.