Documentation

Fields

• mpName :: Text

  Port name (as rendered in HDL)

• mpTypeName :: Text

  Type name (as rendered in HDL)

• mpDirection :: PortDirection

  Port direction (in out inout)

• mpWidth :: Int

  Port width in bits

• mpIsClock :: Bool

  Is this port a clock?

• mpDomain :: Maybe Text

  Domain this port belongs to. This is currently only included for clock, reset, and enable ports. TODO: add to all ports originally defined as a Signal too.

Fields

• manifestHash :: ByteString

  Hash digest of the TopEntity and all its dependencies.

• successFlags :: (Int, Int)

  Compiler flags used to achieve successful compilation:

  • opt_inlineLimit
  • opt_specLimit
• ports :: [ManifestPort]

  Ports in the generated TopEntity.

• componentNames :: [Text]

  Names of all the generated components for the TopEntity (does not include the names of the components of the TestBench accompanying the TopEntity).

  This list is reverse topologically sorted. I.e., a component might depend on any component listed before it, but not after it.

• topComponent :: Text

  Design entry point. This is usually the component annotated with a TopEntity annotation.

• fileNames :: [(FilePath, ByteString)]

  Names and hashes of all the generated files for the TopEntity. Hashes are SHA256.

  This list is reverse topologically sorted. I.e., a component might depend on any component listed before it, but not after it.

• domains :: HashMap Text VDomainConfiguration

  Domains encountered in design

• transitiveDependencies :: [Text]

  Dependencies of this design (fully qualified binder names). Is a transitive closure of all dependencies.

  This list is reverse topologically sorted. I.e., a component might depend on any component listed before it, but not after it.