clash-lib-1.6.6: Clash: a functional hardware description language - As a library
Copyright(C) 2015-2016 University of Twente
2017-2018 Google Inc.
2021-2022 QBayLogic B.V.
LicenseBSD2 (see the file LICENSE)
MaintainerQBayLogic B.V. <devops@qbaylogic.com>
Safe HaskellNone
LanguageHaskell2010

Clash.Backend.Verilog

Contents

Description

Generate Verilog for assorted Netlist datatypes

Synopsis

Documentation

data VerilogState Source #

State for the VerilogM monad:

Instances

Instances details
HasIdentifierSet VerilogState Source # 
Instance details

Defined in Clash.Backend.Verilog

Backend VerilogState Source # 
Instance details

Defined in Clash.Backend.Verilog

Methods

initBackend :: ClashOpts -> VerilogState Source #

hdlKind :: VerilogState -> HDL Source #

primDirs :: VerilogState -> IO [FilePath] Source #

name :: VerilogState -> String Source #

extension :: VerilogState -> String Source #

extractTypes :: VerilogState -> HashSet HWType Source #

genHDL :: ModName -> SrcSpan -> IdentifierSet -> Component -> Ap (State VerilogState) ((String, Doc), [(String, Doc)]) Source #

mkTyPackage :: ModName -> [HWType] -> Ap (State VerilogState) [(String, Doc)] Source #

hdlType :: Usage -> HWType -> Ap (State VerilogState) Doc Source #

hdlHWTypeKind :: HWType -> State VerilogState HWKind Source #

hdlTypeErrValue :: HWType -> Ap (State VerilogState) Doc Source #

hdlTypeMark :: HWType -> Ap (State VerilogState) Doc Source #

hdlRecSel :: HWType -> Int -> Ap (State VerilogState) Doc Source #

hdlSig :: Text -> HWType -> Ap (State VerilogState) Doc Source #

genStmt :: Bool -> State VerilogState Doc Source #

inst :: Declaration -> Ap (State VerilogState) (Maybe Doc) Source #

expr :: Bool -> Expr -> Ap (State VerilogState) Doc Source #

iwWidth :: State VerilogState Int Source #

toBV :: HWType -> Text -> Ap (State VerilogState) Doc Source #

fromBV :: HWType -> Text -> Ap (State VerilogState) Doc Source #

hdlSyn :: State VerilogState HdlSyn Source #

setModName :: ModName -> VerilogState -> VerilogState Source #

setTopName :: Identifier -> VerilogState -> VerilogState Source #

getTopName :: State VerilogState Identifier Source #

setSrcSpan :: SrcSpan -> State VerilogState () Source #

getSrcSpan :: State VerilogState SrcSpan Source #

blockDecl :: Identifier -> [Declaration] -> Ap (State VerilogState) Doc Source #

addIncludes :: [(String, Doc)] -> State VerilogState () Source #

addLibraries :: [Text] -> State VerilogState () Source #

addImports :: [Text] -> State VerilogState () Source #

addAndSetData :: FilePath -> State VerilogState String Source #

getDataFiles :: State VerilogState [(String, FilePath)] Source #

addMemoryDataFile :: (String, String) -> State VerilogState () Source #

getMemoryDataFiles :: State VerilogState [(String, String)] Source #

ifThenElseExpr :: VerilogState -> Bool Source #

aggressiveXOptBB :: State VerilogState AggressiveXOptBB Source #

renderEnums :: State VerilogState RenderEnums Source #

domainConfigurations :: State VerilogState DomainMap Source #

setDomainConfigurations :: DomainMap -> VerilogState -> VerilogState Source #

include :: Monad m => [Text] -> Ap m Doc Source #

uselibs :: Monad m => [Text] -> Ap m Doc Source #

bits :: Lens' s (Maybe (Maybe Int)) -> [Bit] -> Ap (State s) Doc Source #

noEmptyInit :: (Monad m, Semigroup (m Doc)) => m Doc -> m Doc Source #

split ranges

data Range Source #

Range slice, can be contiguous, or split into multiple sub-ranges

Constructors

Contiguous Int Int 
Split [(Int, Int, Provenance)] 

continueWithRange Source #

Arguments

:: [(Int, Int)]

Starts and ends

-> HWType

Type of the projection

-> Range

Range selected so far

-> (Range, HWType) 

Select a sub-range from a range