Copyright	(C) 2015-2016 University of Twente 2017-2018 Google Inc. 2021-2022 QBayLogic B.V.
License	BSD2 (see the file LICENSE)
Maintainer	QBayLogic B.V. <devops@qbaylogic.com>
Safe Haskell	None
Language	Haskell2010

Clash.Backend.SystemVerilog

Description

Generate SystemVerilog for assorted Netlist datatypes

Synopsis

data SystemVerilogState

Documentation

data SystemVerilogState Source #

State for the SystemVerilogM monad:

Instances

Instances details

HasIdentifierSet SystemVerilogState Source #
Instance details Defined in Clash.Backend.SystemVerilog Methods identifierSet :: Lens' SystemVerilogState IdentifierSet Source #
Backend SystemVerilogState Source #
Instance details Defined in Clash.Backend.SystemVerilog Methods initBackend :: ClashOpts -> SystemVerilogState Source # hdlKind :: SystemVerilogState -> HDL Source # primDirs :: SystemVerilogState -> IO [FilePath] Source # name :: SystemVerilogState -> String Source # extension :: SystemVerilogState -> String Source # extractTypes :: SystemVerilogState -> HashSet HWType Source # genHDL :: ModName -> SrcSpan -> IdentifierSet -> Component -> Ap (State SystemVerilogState) ((String, Doc), [(String, Doc)]) Source # mkTyPackage :: ModName -> [HWType] -> Ap (State SystemVerilogState) [(String, Doc)] Source # hdlType :: Usage -> HWType -> Ap (State SystemVerilogState) Doc Source # hdlHWTypeKind :: HWType -> State SystemVerilogState HWKind Source # hdlTypeErrValue :: HWType -> Ap (State SystemVerilogState) Doc Source # hdlTypeMark :: HWType -> Ap (State SystemVerilogState) Doc Source # hdlRecSel :: HWType -> Int -> Ap (State SystemVerilogState) Doc Source # hdlSig :: Text -> HWType -> Ap (State SystemVerilogState) Doc Source # genStmt :: Bool -> State SystemVerilogState Doc Source # inst :: Declaration -> Ap (State SystemVerilogState) (Maybe Doc) Source # expr :: Bool -> Expr -> Ap (State SystemVerilogState) Doc Source # iwWidth :: State SystemVerilogState Int Source # toBV :: HWType -> Text -> Ap (State SystemVerilogState) Doc Source # fromBV :: HWType -> Text -> Ap (State SystemVerilogState) Doc Source # hdlSyn :: State SystemVerilogState HdlSyn Source # setModName :: ModName -> SystemVerilogState -> SystemVerilogState Source # setTopName :: Identifier -> SystemVerilogState -> SystemVerilogState Source # getTopName :: State SystemVerilogState Identifier Source # setSrcSpan :: SrcSpan -> State SystemVerilogState () Source # getSrcSpan :: State SystemVerilogState SrcSpan Source # blockDecl :: Identifier -> [Declaration] -> Ap (State SystemVerilogState) Doc Source # addIncludes :: [(String, Doc)] -> State SystemVerilogState () Source # addLibraries :: [Text] -> State SystemVerilogState () Source # addImports :: [Text] -> State SystemVerilogState () Source # addAndSetData :: FilePath -> State SystemVerilogState String Source # getDataFiles :: State SystemVerilogState [(String, FilePath)] Source # addMemoryDataFile :: (String, String) -> State SystemVerilogState () Source # getMemoryDataFiles :: State SystemVerilogState [(String, String)] Source # ifThenElseExpr :: SystemVerilogState -> Bool Source # aggressiveXOptBB :: State SystemVerilogState AggressiveXOptBB Source # renderEnums :: State SystemVerilogState RenderEnums Source # domainConfigurations :: State SystemVerilogState DomainMap Source # setDomainConfigurations :: DomainMap -> SystemVerilogState -> SystemVerilogState Source #