Generate a simple port_name expression. See:

https://www.hdlworks.com/hdl_corner/vhdl_ref/VHDLContents/PortMap.htm

This function will simply make the left part of a single port map, e.g. Rst in:

Rst => Reset

If you need more complex constructions, e.g.

Q(3 downto 1)

you can build an Expr manually.

Throw away information indicating which constructor fields were filtered due to being void.

Strip as many Void layers as possible. Might still return a Void if the void doesn't contain a hwtype.

Determines if type is a zero-width construct ("void")

Same as isVoid, but on FilteredHWType instead of HWType

Split a normalized term into: a list of arguments, a list of let-bindings, and a variable reference that is the body of the let-binding. Returns a String containing the error if the term was not in a normalized form.

Converts a Core type to a HWType given a function that translates certain builtin types. Errors if the Core type is not translatable.

Same as unsafeCoreTypeToHWTypeM, but discards void filter information

Converts a Core type to a HWType within the NetlistMonad; errors on failure

Same as coreTypeToHWTypeM, but discards void filter information

Converts a Core type to a HWType within the NetlistMonad; Nothing on failure

Constructs error message for unexpected projections out of a type annotated with a custom bit representation.

Helper function of maybeConvertToCustomRepr

Given a map containing custom bit representation, a type, and the same type represented as HWType, convert the HWType to a CustomSP/CustomSum if it has a custom bit representation.

Same as coreTypeToHWType, but discards void filter information

Converts a Core type to a HWType given a function that translates certain builtin types. Returns a string containing the error message when the Core type is not translatable.

Generates original indices in list before filtering, given a list of removed indices.

>>> originalIndices [False, False, True, False]
[0,1,3]

Converts an algebraic Core type (split into a TyCon and its argument) to a HWType.

Determine whether a data constructor has unconstrained existential type variables, i.e. those that cannot be inferred by the (potential) constraints between the existential type variables and universal type variables.

So here we have an example of a constrained existential:

data Vec :: Nat -> Type -> Type where Nil :: Vec 0 a Cons :: forall m . (n ~ m + 1) => a -> Vec m a -> Vec n a

where we can generate a type for m when we know n (by doing `n-1`).

And here is an example of an unconstrained existential:

data SomeSNat where where SomeSNat :: forall m . SNat m -> SomeSNat

where there is no way to generate a type for m from any context.

So why do we care? Because terms need to be completely monomorphic in order to be translated to circuits. And having a topEntity lambda-bound variable with an unconstrained existential type prevents us from achieving a fully monomorphic term.

Simple check if a TyCon is recursively defined.

Note [Look through type families in recursivity check]

Consider:

data SList :: [Type] -> Type where
  SNil  :: SList []
  CSons :: a -> Sing (as :: [k]) -> SList (a:as)

type family Sing [a] = SList [a]

Without looking through type families, we would think that SList is not recursive. This lead to issue #1921

Determines if a Core type is translatable to a HWType given a function that translates certain builtin types.

Determines the bitsize of a type. For types that don't get turned into real values in hardware (string, integer) the size is 0.

Determines the bitsize of the constructor of a type

Gives the HWType corresponding to a term. Returns an error if the term has a Core type that is not translatable to a HWType.

Gives the HWType corresponding to a term. Returns Nothing if the term has a Core type that is not translatable to a HWType.

Uniquely rename all the variables and their references in a normalized term

Produce a Just when predicate is True, else Nothing

Set the name of the binder if the given term is a blackbox requesting a specific name for the result binder. It might return multiple names in case of a multi result primitive.

Render a blackbox given its context. Renders _just_ the blackbox, not any corresponding includes, libraries, and so forth.

Same as idToPort, but * Throws an error if the port is a composite type with a BiSignalIn

Same as idToPort, but: * Throws an error if port is of type BiSignalIn

Make a set of IDs unique; also returns a substitution from old ID to new updated unique ID.

Preserve the complete state before running an action, and restore it afterwards.

Preserve the Netlist _curCompNm,_seenIds when executing a monadic action

Prefix given string before portnames except when this string is empty.

See toPrimitiveType / fromPrimitiveType

Top entities only expose primitive types or types that don't need explicit conversion to a primitive type (i.e., no types from the _types module). This function converts from a custom type to a primitive type if needed.

See HWKind for more info on primitive type kinds.

Top entities only expose primitive types or types that don't need explicit conversion to a primitive type (i.e., no types from the _types module). This function converts from a primitive type to a custom type if needed.

See HWKind for more info on primitive type kinds.

Create port names for the declaration of a top entity. For instantiation see mkTopInstInput.

Create a Vector chain for a list of Identifiers

Create a RTree chain for a list of Identifiers

Strips one or more layers of attributes from a HWType; stops at first non-Annotated. Accumulates all attributes of nested annotations.

Create output port names for the declaration of a top entity. For instantiation see mkTopInstOutput.

Instantiate a TopEntity, and add the proper type-conversions where needed

Generate input port(s) associated with a single argument for an instantiation of a top entity. This function composes the input ports into a single signal and returns its name.

Consider the following type signature:

  f :: Signal dom (Vec 6 A) `Annotate` Attr "keep"
    -> Signal dom (Vec 6 B)

What does the annotation mean, considering that Clash will split these vectors into multiple in- and output ports? Should we apply the annotation to all individual ports? How would we handle pin mappings? For now, we simply throw an error. This is a helper function to do so.

Generate output port(s) for an instantiation of a top entity. This function combines all output ports into a signal identifier and returns its name.

Try to merge nested modifiers into a single modifier, needed by the VHDL and SystemVerilog backend.

Determines if any type variables (exts) are bound in any of the given type or term variables (tms). It's currently only used to detect bound existentials, hence the name.

Run a NetlistMonad computation in the context of the given source ticks and name modifier ticks

Add the pre- and suffix names in the current environment to the given identifier

Errors expandTopEntity might yield

Same as expandTopEntity, but also adds identifiers to the identifier set of the monad.

Take a top entity and expand its port names. I.e., make sure that every port that should be generated in the HDL is part of the data structure.

Take a top entity and expand its port names. I.e., make sure that every port that should be generated in the HDL is part of the data structure. It works on FilteredHWType in order to generate stable port names.