Create a blackBoxHaskell primitive. To be used as part of an annotation:

{--}

The state of a block. Contains a list of declarations and a the backend state.

A typed expression.

Run a block declaration.

Instantiate a component/entity in a block state.

Wires the two given TExprs together using a newly declared signal with (exactly) the given name sigNm. The new signal has an annotated type, using the given attributes.

Construct a fully defined BitVector literal

A literal that can be used for hdl attributes. It has a Num and IsString instances for convenience.

The high literal bit.

The low literal bit.

Create an n-tuple of TExpr

Create a vector of TExprs

The TExp inputs from a blackbox context.

The TExp result of a blackbox context.

Try to get the literal string value of an expression.

Try to get the literal bool value of an expression.

Try to get the literal nat value of an expression.

Extract the elements of a tuple expression and return expressions to them. These new expressions are given unique names and get declared the block scope.

Extract the elements of a vector expression and return expressions to them. If given expression is not an identifier, an intermediate variable will be used to assign the given expression to which is subsequently indexed.

Assign an input bitvector to an expression. Declares a new bitvector if the expression is not already a bitvector.

Assign an output bitvector to an expression. Declares a new bitvector if the expression is not already a bitvector.

Convert a bool to a bit.

Use to create an output Bool from a Bit. The expression given must be the identifier of the bool you wish to get assigned. Returns a reference to a declared Bit that should get assigned by something (usually the output port of an entity).

Used to create an output Bool from a BitVector of given size. Works in a similar way to boolFromBit above.

Used to create an output Unsigned from a BitVector of given size. Works in a similar way to boolFromBit above.

TODO: Implement for (System)Verilog

Used to create an output Bool from a number of Bits, using conjunction. Similarly to untuple, it returns a list of references to declared values (the inputs to the function) which should get assigned by something---usually output ports of an entity.

TODO: Implement for (System)Verilog

And together (&&) two expressions, assigning it to a new identifier.

Negate (not) an expression, assigning it to a new identifier.

Creates a BV that produces the following vhdl:

   (0 to n => ARG)

TODO: Implement for (System)Verilog

Creates a BV that produces the following vhdl:

   std_logic_vector(resize(ARG, Size))

TODO: Implement for (System)Verilog

Allows assignment of a port to be "open"

Get an identifier to an expression, creating a new assignment if necessary.