clash-lib-1.2.2: CAES Language for Synchronous Hardware - As a Library

Copyright	(C) 2015-2016 University of Twente 2017-2018 Google Inc.
License	BSD2 (see the file LICENSE)
Maintainer	Christiaan Baaij <christiaan.baaij@gmail.com>
Safe Haskell	None
Language	Haskell2010

Clash.Backend.SystemVerilog

Description

Generate SystemVerilog for assorted Netlist datatypes

Synopsis

data SystemVerilogState

Documentation

data SystemVerilogState Source #

State for the SystemVerilogM monad:

Instances

Instances details

Backend SystemVerilogState Source #

Instance details

Defined in Clash.Backend.SystemVerilog

Methods

initBackend :: Int -> HdlSyn -> Bool -> Maybe (Maybe Int) -> SystemVerilogState Source #

hdlKind :: SystemVerilogState -> HDL Source #

primDirs :: SystemVerilogState -> IO [FilePath] Source #

name :: SystemVerilogState -> String Source #

extension :: SystemVerilogState -> String Source #

extractTypes :: SystemVerilogState -> HashSet HWType Source #

genHDL :: Identifier -> SrcSpan -> HashMap Identifier Word -> Component -> Mon (State SystemVerilogState) ((String, Doc), [(String, Doc)]) Source #

mkTyPackage :: Identifier -> [HWType] -> Mon (State SystemVerilogState) [(String, Doc)] Source #

hdlType :: Usage -> HWType -> Mon (State SystemVerilogState) Doc Source #

hdlTypeErrValue :: HWType -> Mon (State SystemVerilogState) Doc Source #

hdlTypeMark :: HWType -> Mon (State SystemVerilogState) Doc Source #

hdlRecSel :: HWType -> Int -> Mon (State SystemVerilogState) Doc Source #

hdlSig :: Text -> HWType -> Mon (State SystemVerilogState) Doc Source #

genStmt :: Bool -> State SystemVerilogState Doc Source #

inst :: Declaration -> Mon (State SystemVerilogState) (Maybe Doc) Source #

expr :: Bool -> Expr -> Mon (State SystemVerilogState) Doc Source #

iwWidth :: State SystemVerilogState Int Source #

toBV :: HWType -> Text -> Mon (State SystemVerilogState) Doc Source #

fromBV :: HWType -> Text -> Mon (State SystemVerilogState) Doc Source #

hdlSyn :: State SystemVerilogState HdlSyn Source #

mkIdentifier :: State SystemVerilogState (IdType -> Identifier -> Identifier) Source #

extendIdentifier :: State SystemVerilogState (IdType -> Identifier -> Identifier -> Identifier) Source #

setModName :: ModName -> SystemVerilogState -> SystemVerilogState Source #

setSrcSpan :: SrcSpan -> State SystemVerilogState () Source #

getSrcSpan :: State SystemVerilogState SrcSpan Source #

blockDecl :: Text -> [Declaration] -> Mon (State SystemVerilogState) Doc Source #

unextend :: State SystemVerilogState (Identifier -> Identifier) Source #

addIncludes :: [(String, Doc)] -> State SystemVerilogState () Source #

addLibraries :: [Text] -> State SystemVerilogState () Source #

addImports :: [Text] -> State SystemVerilogState () Source #

addAndSetData :: FilePath -> State SystemVerilogState String Source #

getDataFiles :: State SystemVerilogState [(String, FilePath)] Source #

addMemoryDataFile :: (String, String) -> State SystemVerilogState () Source #

getMemoryDataFiles :: State SystemVerilogState [(String, String)] Source #

seenIdentifiers :: Lens' SystemVerilogState (HashMap Identifier Word) Source #

ifThenElseExpr :: SystemVerilogState -> Bool Source #