Changelog for clash-lib-1.0.1

Changelog for the Clash project

1.0.2

Fixes issues:
- #895: VHDL type error when generating Maybe (Vec 2 (Signed 8), Index 1)
- #869: PLL is duplicated in Blinker.hs example
Small fixes without issue reports:
- Adds '--enable-shared-executables' for nix builds; this should make Clash run much faster (#894)
- Fix blackbox issues causing Clash to generate invalid HDL (#865)
- Error on unparsed trailing garbage in JSON "files"
Deprecations & removals:
- Reset and Enable constructors are now only exported from Clash.Signal.Internal

1.0.1 October 17th 2019

Fixes issues:
- #810: Verilog backend now correctly specifies type of BitVector 1
- #811: Improve module load behavior in clashi
- #439: Template Haskell splices and TopEntity annotations can now be used in clashi
- #818: Fixed various mistakes in tutorial
- #662: Clash will now constant specialize partially constant constructs
- #700: Check work content of expression in cast before warning users. Should eliminate a lot of (superfluous) warnings about "specializing on non work-free cast"s.
- #837: Blackboxes will now report clearer error messages if they're given unexpected arguments.
Small fixes without issue reports:
- Fix bug in rnfX defined for Down (814fd52)
- Report blackbox name when encountering an error in 'setSym' (#858)

1.0.0 September 3rd 2019

10x - 50x faster compile times
New features:
- API changes: check the migration guide at the end of Clash.Tutorial
- All memory elements now have an (implicit) enable line; "Gated" clocks have been removed as the clock wasn't actually gated, but implemented as an enable line.
- Circuit domains are now configurable in:
  - (old) The clock period
  - (new) Clock edge on which memory elements latch their inputs (rising edge or falling edge)
  - (new) Whether the reset port of a memory element is level sensitive (asynchronous reset) or edge sensitive (synchronous reset)
  - (new) Whether the reset port of a memory element is active-high or active-low (negated reset)
  - (new) Whether memory element power on in a configurable/defined state (common on FPGAs) or in an undefined state (ASICs)
  - See the blog post on this new feature
- Data types can now be given custom bit-representations: http://hackage.haskell.org/package/clash-prelude/docs/Clash-Annotations-BitRepresentation.html
- Annotate expressions with attributes that persist in the generated HDL, e.g. synthesis directives: http://hackage.haskell.org/package/clash-prelude/docs/Clash-Annotations-SynthesisAttributes.html
- Control (System)Verilog module instance, and VHDL entity instantiation names in generated code: http://hackage.haskell.org/package/clash-prelude/docs/Clash-Magic.html
- Much improved infrastructure for handling of unknown values: defined spine, but unknown leafs: http://hackage.haskell.org/package/clash-prelude/docs/Clash-XException.html#t:NFDataX
- Experimental: Multiple hidden clocks. Can be enabled by compiling clash-prelude with -fmultiple-hidden
- Experimental: Limited GADT support (pattern matching on vectors, or custom GADTs as longs as their usage can be statically removed; no support of recursive GADTs)
- Experimental: Use regular Haskell functions to generate HDL black boxes for primitives (in an addition to existing string templates for HDL black boxes) See for example: http://hackage.haskell.org/package/clash-lib/docs/Clash-Primitives-Intel-ClockGen.html
Fixes issues:
- #316
- #319
- #323
- #324
- #329
- #331
- #332
- #335
- #348
- #349
- #350
- #351
- #352
- #353
- #358
- #359
- #363
- #364
- #365
- #371
- #372
- #373
- #378
- #380
- #381
- #382
- #383
- #387
- #393
- #396
- #398
- #399
- #401
- #403
- #407
- #412
- #413
- #420
- #422
- #423
- #424
- #438
- #450
- #452
- #455
- #460
- #461
- #463
- #468
- #475
- #476
- #500
- #507
- #512
- #516
- #517
- #526
- #556
- #560
- #566
- #567
- #569
- #573
- #575
- #581
- #582
- #586
- #588
- #591
- #596
- #601
- #607
- #629
- #637
- #644
- #647
- #661
- #668
- #677
- #678
- #682
- #691
- #703
- #713
- #715
- #727
- #730
- #736
- #738

0.99.3 July 28th 2018

Fixes bugs:
- Evaluator recognizes Bit literals #329
- Use existential type-variables in context of GADT pattern match
- Do not create zero-bit temporary variables in generated HDL
- Use correct arguments in nested primitives #323
- Zero-constructor data type needs 0 bits #238
- Create empty component when result needs 0 bits
- Evaluator performs BigNat arithmetic
Features:
- Bundle and BitPack instances up to and including 62-tuples
- Handle undefined writes to RAM properly
- Handle undefined clock enables properly

0.99.1 May 12th 2018

Allow ~NAME[N] tag inside ~GENSYM[X]
Support HDL record selector generation #313
InlinePrimitive support: specify HDL primitives inline with Haskell code
Support for ghc-typelits-natnormalise-0.6.1
Lift instances for TopEntity and PortName
InlinePrimitive support: specify HDL primitives inline with Haskell code

0.99 March 31st 2018

New features:
- Major API overhaul: check the migration guide at the end of Clash.Tutorial
- New features:
  - Explicit clock and reset arguments
  - Rename CLaSH to Clash
  - Implicit/Hidden clock and reset arguments using a combination of reflection and ImplicitParams.
  - Large overhaul of TopEntity annotations
  - PLL and other clock sources can now be instantiated using regular functions: Clash.Intel.ClockGen and Clash.Xilinx.ClockGen.
  - DDR registers:
    - Generic/ASIC: Clash.Explicit.DDR
    - Intel: Clash.Intel.DDR
    - Xilinx: Clash.Intel.Xilinx
- Bit is now a newtype instead of a type synonym and will be mapped to a HDL scalar instead of an array of one (e.g std_logic instead of std_logic_vector(0 downto 0))
- Hierarchies with multiple synthesisable boundaries by allowing more than one function in scope to have a Synthesize annotation.
  - Local caching of functions with a Synthesize annotation
- Bit type is mapped to a HDL scalar type (e.g. std_logic in VHDL)
- Improved name preservation
- Zero-bit values are filtered out of the generated HDL
- Improved compile-time computation
Many bug fixes

Older versions

Check out: