clash-lib-0.99.2: CAES Language for Synchronous Hardware - As a Library

Copyright	(C) 2015-2016 University of Twente 2017 Google Inc.
License	BSD2 (see the file LICENSE)
Maintainer	Christiaan Baaij <christiaan.baaij@gmail.com>
Safe Haskell	None
Language	Haskell2010

Clash.Backend.VHDL

Description

Generate VHDL for assorted Netlist datatypes

Synopsis

data VHDLState

Documentation

data VHDLState Source #

State for the VHDLM monad:

Instances

Backend VHDLState Source #

Instance details

Defined in Clash.Backend.VHDL

Methods

initBackend :: Int -> HdlSyn -> VHDLState Source #

hdlKind :: VHDLState -> HDL Source #

primDirs :: VHDLState -> IO [FilePath] Source #

name :: VHDLState -> String Source #

extension :: VHDLState -> String Source #

extractTypes :: VHDLState -> HashSet HWType Source #

genHDL :: String -> SrcSpan -> Component -> Mon (State VHDLState) ((String, Doc), [(String, Doc)]) Source #

mkTyPackage :: String -> [HWType] -> Mon (State VHDLState) [(String, Doc)] Source #

hdlType :: Usage -> HWType -> Mon (State VHDLState) Doc Source #

hdlTypeErrValue :: HWType -> Mon (State VHDLState) Doc Source #

hdlTypeMark :: HWType -> Mon (State VHDLState) Doc Source #

hdlRecSel :: HWType -> Int -> Mon (State VHDLState) Doc Source #

hdlSig :: Text -> HWType -> Mon (State VHDLState) Doc Source #

genStmt :: Bool -> State VHDLState Doc Source #

inst :: Declaration -> Mon (State VHDLState) (Maybe Doc) Source #

expr :: Bool -> Expr -> Mon (State VHDLState) Doc Source #

iwWidth :: State VHDLState Int Source #

toBV :: HWType -> Text -> Mon (State VHDLState) Doc Source #

fromBV :: HWType -> Text -> Mon (State VHDLState) Doc Source #

hdlSyn :: State VHDLState HdlSyn Source #

mkIdentifier :: State VHDLState (IdType -> Identifier -> Identifier) Source #

extendIdentifier :: State VHDLState (IdType -> Identifier -> Identifier -> Identifier) Source #

setModName :: ModName -> VHDLState -> VHDLState Source #

setSrcSpan :: SrcSpan -> State VHDLState () Source #

getSrcSpan :: State VHDLState SrcSpan Source #

blockDecl :: Text -> [Declaration] -> Mon (State VHDLState) Doc Source #

unextend :: State VHDLState (Identifier -> Identifier) Source #

addInclude :: (String, Doc) -> State VHDLState () Source #

addLibraries :: [Text] -> State VHDLState () Source #

addImports :: [Text] -> State VHDLState () Source #