Documentation

Fields

• name :: !Text

  Name of the primitive

• outputReg :: Bool

  Verilog only: whether the result should be a reg(True) or wire (False); when not specified in the .json file, the value will default to False (i.e. wire).

• library :: [a]

  VHDL only: add library declarations for the given names

• imports :: [a]

  VHDL only: add use declarations for the given names

• include :: Maybe ((Text, Text), a)

  Create a file to be included with the generated primitive. The fields are ((name, extension), content), where content is a template of the file Defaults to Nothing when not specified in the .json file

• template :: !(Either a a)

  Either a declaration or an expression template.

Fields

• name :: !Text

  Name of the primitive

• primType :: !Text

  Additional information