| randomDAG | Verismith.Circuit.Random, Verismith.Circuit, Verismith |
| randomMod | Verismith.Generate, Verismith |
| Range | |
| 1 (Type/Class) | Verismith.Verilog.AST |
| 2 (Data Constructor) | Verismith.Verilog.AST |
| range | Verismith.Generate |
| rangeLSB | Verismith.Verilog.AST |
| rangeMSB | Verismith.Verilog.AST |
| RangeSelect | Verismith.Verilog.AST, Verismith.Verilog, Verismith |
| rDups | Verismith.Circuit.Random, Verismith.Circuit, Verismith |
| rDupsCirc | Verismith.Circuit.Random, Verismith.Circuit, Verismith |
| Reduce | Verismith.OptParser, Verismith |
| reduce | Verismith.Reduce |
| reduceFilename | Verismith.OptParser, Verismith |
| reduceRerun | Verismith.OptParser, Verismith |
| reduceScript | Verismith.OptParser, Verismith |
| reduceSimIc | Verismith.Reduce |
| reduceSynth | Verismith.Reduce |
| reduceSynthesis | Verismith.Reduce |
| reduceSynthesiserDesc | Verismith.OptParser, Verismith |
| reduceTop | Verismith.OptParser, Verismith |
| reduceWithScript | Verismith.Reduce |
| reduce_ | Verismith.Reduce |
| reducTime | Verismith.Report, Verismith |
| Reg | Verismith.Verilog.AST, Verismith.Verilog, Verismith |
| reg | Verismith.Verilog.Internal |
| regConc | Verismith.Verilog.AST, Verismith.Verilog, Verismith |
| RegConcat | Verismith.Verilog.AST, Verismith.Verilog, Verismith |
| regDecl | Verismith.Verilog.Internal |
| RegExpr | Verismith.Verilog.AST, Verismith.Verilog, Verismith |
| regExpr | Verismith.Verilog.AST, Verismith.Verilog, Verismith |
| regExprId | Verismith.Verilog.AST, Verismith.Verilog, Verismith |
| RegId | Verismith.Verilog.AST, Verismith.Verilog, Verismith |
| regId | Verismith.Verilog.AST, Verismith.Verilog, Verismith |
| RegSize | Verismith.Verilog.AST, Verismith.Verilog, Verismith |
| regSizeId | Verismith.Verilog.AST, Verismith.Verilog, Verismith |
| regSizeRange | Verismith.Verilog.AST, Verismith.Verilog, Verismith |
| removeConstInConcat | Verismith.Reduce |
| removeDecl | Verismith.Reduce |
| removeId | Verismith.Verilog.Mutate |
| renameSource | Verismith.Tool.Internal |
| render | Verismith.Verilog.CodeGen |
| replace | |
| 1 (Function) | Verismith.Tool.Internal |
| 2 (Function) | Verismith.Verilog.Mutate |
| Replacement | Verismith.Reduce |
| replaceMods | Verismith.Tool.Internal |
| resize | Verismith.Verilog.Eval |
| resizePort | Verismith.Generate |
| Result | Verismith.Result |
| ResultSh | Verismith.Tool.Internal |
| resultSh | Verismith.Tool.Internal |
| ResultT | |
| 1 (Type/Class) | Verismith.Result |
| 2 (Data Constructor) | Verismith.Result |
| rootPath | Verismith.Tool.Internal |
| runEquiv | Verismith.Tool.Yosys, Verismith.Tool, Verismith |
| runEquivalence | Verismith |
| runEquivYosys | Verismith.Tool.Yosys |
| runFuzz | Verismith.Fuzz, Verismith |
| runReduce | Verismith |
| runResultT | Verismith.Result |
| runSim | Verismith.Tool.Internal, Verismith.Tool, Verismith |
| runSimIc | Verismith.Tool.Icarus |
| runSimIcEC | Verismith.Tool.Icarus |
| runSimulation | Verismith |
| runSimWithFile | Verismith.Tool.Internal |
| runSynth | Verismith.Tool.Internal, Verismith.Tool, Verismith |