riscv-isa-0.1.0.0: Haskell representation of the RISC-V instruction set architecture

Safe HaskellNone
LanguageHaskell2010

RiscV.RV32I

Contents

Synopsis

Documentation

data Register Source #

Register 1-31 are general-purpose registers holding integer values.

Register 0 is hardwired to the constant 0.

Constructors

X0 
X1 
X2 
X3 
X4 
X5 
X6 
X7 
X8 
X9 
X10 
X11 
X12 
X13 
X14 
X15 
X16 
X17 
X18 
X19 
X20 
X21 
X22 
X23 
X24 
X25 
X26 
X27 
X28 
X29 
X30 
X31 

Integer Register-Immediate Instructions

Integer Register-Register Instructions

Control Transfer Instructions

Load and Store Instructions

data Width Source #

Constructors

Byte 
Half 
Word 

Instances

Memory Synchronization Instructions

Control and Status Register Instructions

data CSRType Source #

Control and status register instruction type

Constructors

ReadWrite 
ReadSet 
ReadClear 

Environment Call and Breakpoints

Word Types

newtype Word5 Source #

Constructors

Word5 Word8 

Instances