Copyright | (c) David Cox 2021 |
---|---|
License | BSD-3-Clause |
Maintainer | standardsemiconductor@gmail.com |
Safe Haskell | None |
Language | Haskell2010 |
Documentation
:: HiddenClockResetEnable dom | |
=> BitVector 32 | start address |
-> Signal dom (BitVector 32) | core input, from memory/peripherals |
-> FromCore dom | core output |
RISC-V Core
Core outputs
Memory bus
Lion has a shared instruction/memory bus
Instances
Eq ToMem Source # | |
Show ToMem Source # | |
Generic ToMem Source # | |
NFDataX ToMem Source # | |
type Rep ToMem Source # | |
Defined in Lion.Pipe type Rep ToMem = D1 ('MetaData "ToMem" "Lion.Pipe" "lion-0.1.0.0-BYNHz6t7z8e8tkdinpAB9M" 'False) (C1 ('MetaCons "InstrMem" 'PrefixI 'False) (S1 ('MetaSel ('Nothing :: Maybe Symbol) 'NoSourceUnpackedness 'NoSourceStrictness 'DecidedLazy) (Rec0 (BitVector 32))) :+: C1 ('MetaCons "DataMem" 'PrefixI 'False) (S1 ('MetaSel ('Nothing :: Maybe Symbol) 'NoSourceUnpackedness 'NoSourceStrictness 'DecidedLazy) (Rec0 (BitVector 32)) :*: (S1 ('MetaSel ('Nothing :: Maybe Symbol) 'NoSourceUnpackedness 'NoSourceStrictness 'DecidedLazy) (Rec0 (BitVector 4)) :*: S1 ('MetaSel ('Nothing :: Maybe Symbol) 'NoSourceUnpackedness 'NoSourceStrictness 'DecidedLazy) (Rec0 (Maybe (BitVector 32)))))) |