lion-0.1.0.0: RISC-V Core
Copyright(c) David Cox 2021
LicenseBSD-3-Clause
Maintainerstandardsemiconductor@gmail.com
Safe HaskellNone
LanguageHaskell2010

Lion.Core

Description

The Lion core is a 32-bit RISC-V processor written in Haskell using Clash. Note, all peripherals and memory must have single cycle latency. See lion-soc for an example of using the Lion core in a system.

Synopsis

Documentation

core Source #

Arguments

:: HiddenClockResetEnable dom 
=> BitVector 32

start address

-> Signal dom (BitVector 32)

core input, from memory/peripherals

-> FromCore dom

core output

RISC-V Core

data FromCore dom Source #

Core outputs

Constructors

FromCore 

Fields

toMem :: forall dom. Lens' (FromCore dom) (Signal dom (Maybe ToMem)) Source #

toRvfi :: forall dom. Lens' (FromCore dom) (Signal dom Rvfi) Source #

data ToMem Source #

Memory bus

Lion has a shared instruction/memory bus

Constructors

InstrMem

instruction read

Fields

DataMem

data access

Fields

Instances

Instances details
Eq ToMem Source # 
Instance details

Defined in Lion.Pipe

Methods

(==) :: ToMem -> ToMem -> Bool #

(/=) :: ToMem -> ToMem -> Bool #

Show ToMem Source # 
Instance details

Defined in Lion.Pipe

Methods

showsPrec :: Int -> ToMem -> ShowS #

show :: ToMem -> String #

showList :: [ToMem] -> ShowS #

Generic ToMem Source # 
Instance details

Defined in Lion.Pipe

Associated Types

type Rep ToMem :: Type -> Type #

Methods

from :: ToMem -> Rep ToMem x #

to :: Rep ToMem x -> ToMem #

NFDataX ToMem Source # 
Instance details

Defined in Lion.Pipe

type Rep ToMem Source # 
Instance details

Defined in Lion.Pipe