lambdaya-bus-0.0.0.2: Fpga bus core and serialization for RedPitaya

CopyrightLuka Rahne
LicenseLGPL-3 (see the file LICENSE)
MaintainerLuka Rahne <luka.rahne@gmail.com>
Safe HaskellNone
LanguageHaskell2010

System.RedPitaya.Bus.RedPitayaSimple

Description

 

Synopsis

Documentation

data ReadWrite Source #

Constructors

Read 
Write 

defTopRedPitayaSimple :: TopEntity Source #

this definition should be used to define bus that can be directly build with fpga core defined in redpitaya branch clash https://github.com/ra1u/RedPitaya/tree/clash

rpSimpleBind :: (Signal BusIn -> Signal BusOut) -> Signal RpBusSysIn -> Signal RpBusSysOut Source #

provide redPitayaSimple interface ovet simplified bus where redPitayaSimple is bus as defined https://github.com/ra1u/RedPitaya/blob/clash/fpga/rtl/red_pitaya_top.v

addrLow :: Signal BusIn -> Signal BusIn Source #

remove away MSB part of address with page info away