Portability	portable
Stability	provisional
Maintainer	eocallaghan@alterapraxis.com
Safe Haskell	Trustworthy

LibBladeRF.Gpio

Description

This module deals with GPIO configuration handling.

The following example illustrates the setup of GPIO's for timestamping in the usual, read, modify, write sequence:

   gpios <- bladeRFConfigGPIORead dev
   case gpios of
     Left e -> throwIO e
     Right gpios -> do
       putStrLn "========= GPIO Dump ========="
       mapM_ putStrLn $ debugBladeRFGPIOFlags gpios
       bladeRFConfigGPIOWrite dev $ GPIO_TIMESTAMP : gpios

Documentation

data BladeRFGPIOFlags Source

BladeRF GPIO Flag Type.

Constructors

GPIO_LMS_RX_ENABLE	Enable LMS receive. N.B. This bit is set/cleared by `bladeRFEnableModule`
GPIO_LMS_TX_ENABLE	Enable LMS transmit. N.B. This bit is set/cleared by `bladeRFEnableModule`
GPIO_TX_LB_ENABLE	Switch to use TX low band (300MHz - 1.5GHz). N.B. This is set using `bladeRFSetFrequency`.
GPIO_TX_HB_ENABLE	Switch to use TX high band (1.5GHz - 3.8GHz). N.B. This is set using `bladeRFSetFrequency`.
GPIO_COUNTER_ENABLE	Counter mode enable. Setting this bit to 1 instructs the FPGA to replace the (I, Q) pair in sample data with an incrementing, little-endian, 32-bit counter value. A 0 in bit specifies that sample data should be sent (as normally done). This feature is useful when debugging issues involving dropped samples.
GPIO_RX_LB_ENABLE	Switch to use RX low band (300M - 1.5GHz). N.B. This is set using `bladeRFSetFrequency`.
GPIO_RX_HB_ENABLE	Switch to use RX high band (1.5GHz - 3.8GHz). N.B. This is set using `bladeRFSetFrequency`.
GPIO_FEATURE_SMALL_DMA_XFER	This GPIO bit configures the FPGA to use smaller DMA transfers (256 cycles instead of 512). This is required when the device is not connected at Super Speed (i.e., when it is connected at High Speed). However, the caller need not set this in `bladeRFConfigGPIOWrite` calls. The library will set this as needed; callers generally do not need to be concerned with setting/clearing this bit.
GPIO_TIMESTAMP	Enable-bit for timestamp counter in the FPGA.
GPIO_TIMESTAMP_DIV2	Timestamp 2x divider control. By default (value = 0), the sample counter is incremented with I and Q, yielding two counts per sample. Set this bit to 1 to enable a 2x timestamp divider, effectively achieving 1 timestamp count per sample.

Instances

Enum BladeRFGPIOFlags
Eq BladeRFGPIOFlags

debugBladeRFGPIOFlags :: [BladeRFGPIOFlags] -> [String]Source

Useful helper function to decode GPIO flags into strings

Example:

    gpios <- bladeRFConfigGPIORead dev
    case gpios of
      Left e -> throwIO e
      Right g -> mapM_ putStrLn $ debugBladeRFGPIOFlags g

bladeRFConfigGPIORead Source

Arguments

:: DeviceHandle	Device handle
-> IO (BladeRFReturnType [BladeRFGPIOFlags])	Read data

Read a configuration GPIO register.

bladeRFConfigGPIOWrite Source

Arguments

:: DeviceHandle	Device handle
-> [BladeRFGPIOFlags]	Data to write to GPIO register
-> IO (BladeRFReturnType ())

Write a configuration GPIO register.

Callers should be sure to perform a read-modify-write sequence to avoid accidentally clearing other GPIO bits that may be set by the library internally.