clashilator: Automated Clash to Verilator bridge

[ development, hardware, library, mit, program ] [ Propose Tags ]

Code generator and Setup.hs hooks to generate a Verilator simulation and access it from Clash

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Versions [RSS] 0.1.0, 0.1.1, 0.1.2,, 0.1.3, 0.1.4
Dependencies aeson (>=1.5 && <3.0), base (>=4.14 && <5), Cabal (>=3.2.1 && <3.9), clash-ghc (>=1.4.2 && <2.0), clash-lib (>=1.4.2 && <2.0), containers, filepath, ghc, lens, optparse-applicative, shake, stache (>=2.3 && <2.4), text, unordered-containers [details]
License MIT
Author Gergő Érdi
Category Hardware, Development
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Source repo head: git clone
Uploaded by GergoErdi at 2024-04-20T10:21:37Z
Executables clashilator
Downloads 432 total (16 in the last 30 days)
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Status Docs available [build log]
Last success reported on 2024-04-20 [all 1 reports]

Readme for clashilator-0.1.4

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Clashilator: Automated Clash - Verilator integration

This package provides Cabal Setup.hs functionality to automatically integrate Verilator into your Clash project.


Suppose you have a Clash circuit that you want to simulate using Verilator, and then write Haskell code to interact with that simulation. If your Clash code looks like this:

    :: "CLK" ::: Clock System
    -> "FOO" ::: Signal System Bit
    -> "BAR" ::: Signal System (Unsigned 4)
    -> ( "BAZ"  ::: Signal System (Unsigned 10)
       , "QUUX" ::: Signal System Bit
topEntity = ...
makeTopEntity 'topEntity

and you put this in your Cabal file (x-clashilator-clock can be omitted if you have only a single clock):

  setup-depends: clashilator

executable MySim
  main-is: simulator.hs
  x-clashilator-clock: CLK
  x-clashilator-top-is: MyCircuit

then in your simulator.hs, you can import the "virtual" module Clash.Clashilator.FFI which provides the following definitions:

    { iFOO :: Bit
    , iBAR :: Word8
    deriving (Show)
instance Storable INPUT

    { oBAZ :: Word16
    , oQUUX :: Bit
    deriving (Show)
instance Storable OUTPUT

data Sim

simInit     :: IO (Ptr Sim)
simShutdown :: Ptr Sim -> IO ()
simStep     :: Ptr Sim -> Ptr INPUT -> Ptr OUTPUT -> IO ()

Note that input and output buses are represented as the smallest possible Word type, to improve marshalling cost when crossing the Haskell-C++ barrier.