Copyright | (C) 2019 Myrtle Software Ltd |
---|---|
License | BSD2 (see the file LICENSE) |
Maintainer | QBayLogic B.V. <devops@qbaylogic.com> |
Safe Haskell | None |
Language | Haskell2010 |
See Clash.Explicit.Verification for an introduction.
The verification API is currently experimental and subject to change.
Synopsis
- data Assertion (dom :: Domain)
- data Property (dom :: Domain)
- data RenderAs
- = PSL
- | SVA
- | AutoRenderAs
- | YosysFormal
- name :: Text -> Signal dom Bool -> Assertion dom
- lit :: Bool -> Assertion dom
- not :: AssertionValue dom a => a -> Assertion dom
- and :: (AssertionValue dom a, AssertionValue dom b) => a -> b -> Assertion dom
- or :: (AssertionValue dom a, AssertionValue dom b) => a -> b -> Assertion dom
- implies :: (AssertionValue dom a, AssertionValue dom b) => a -> b -> Assertion dom
- next :: AssertionValue dom a => a -> Assertion dom
- nextN :: AssertionValue dom a => Word -> a -> Assertion dom
- before :: (AssertionValue dom a, AssertionValue dom b) => a -> b -> Assertion dom
- timplies :: (AssertionValue dom a, AssertionValue dom b) => a -> b -> Assertion dom
- timpliesOverlapping :: (AssertionValue dom a, AssertionValue dom b) => a -> b -> Assertion dom
- always :: AssertionValue dom a => a -> Assertion dom
- never :: AssertionValue dom a => a -> Assertion dom
- eventually :: AssertionValue dom a => a -> Assertion dom
- assert :: AssertionValue dom a => a -> Property dom
- cover :: AssertionValue dom a => a -> Property dom
- check :: (KnownDomain dom, HiddenClock dom, HiddenReset dom) => Text -> RenderAs -> Property dom -> Signal dom AssertionResult
- checkI :: (KnownDomain dom, HiddenClock dom, HiddenReset dom) => Text -> RenderAs -> Property dom -> Signal dom a -> Signal dom a
- hideAssertion :: Signal dom AssertionResult -> Signal dom a -> Signal dom a
Types
data Assertion (dom :: Domain) Source #
Instances
AssertionValue dom (Assertion dom) Source # | Result of a property specification |
Defined in Clash.Verification.Internal toAssertionValue :: Assertion dom -> Assertion dom Source # |
Render target for HDL
PSL | Property Specification Language |
SVA | SystemVerilog Assertions |
AutoRenderAs | Use SVA for SystemVerilog, PSL for others |
YosysFormal | Yosys Formal Extensions for Verilog and SystemVerilog. See: https://symbiyosys.readthedocs.io/en/latest/verilog.html and https://symbiyosys.readthedocs.io/en/latest/verific.html Falls back to PSL for VHDL, however currently Clash's PSL syntax isn't suported by GHDL+SymbiYosys; |
Bootstrapping functions
name :: Text -> Signal dom Bool -> Assertion dom Source #
Convert a signal to a cv expression with a name hint. Clash will try its
best to use this name in the rendered assertion, but might run into
collisions. You can skip using name
altogether. Clash will then try its
best to get a readable name from context.
Functions to build a PSL/SVA expressions
not :: AssertionValue dom a => a -> Assertion dom Source #
Truth table for not
:
a | not a ------------ True | False False | True
and :: (AssertionValue dom a, AssertionValue dom b) => a -> b -> Assertion dom Source #
Truth table for and
:
a | b | a `and` b --------------|---------- False | False | False False | True | False True | False | False True | True | True
or :: (AssertionValue dom a, AssertionValue dom b) => a -> b -> Assertion dom Source #
Truth table for or
:
a | b | a `or` b --------------|--------- False | False | False False | True | True True | False | True True | True | True
implies :: (AssertionValue dom a, AssertionValue dom b) => a -> b -> Assertion dom Source #
Truth table for implies
:
a | b | a `implies` b --------------|-------------- False | False | True False | True | True True | False | False True | True | True
next :: AssertionValue dom a => a -> Assertion dom Source #
Truth table for next
:
a[n] | a[n+1] | a `implies` next a ---------------|------------------- False | False | True False | True | True True | False | False True | True | True
where a[n] represents the value of a
at cycle n
and a[n+1]
represents
the value of a
at cycle n+1
. Cycle n is an arbitrary cycle.
nextN :: AssertionValue dom a => Word -> a -> Assertion dom Source #
Truth table for nextN
:
a[n] | a[n+m] | a `implies` next m a ---------------|--------------------- False | False | True False | True | True True | False | False True | True | True
where a[n] represents the value of a
at cycle n
and a[n+m] represents
the value of a
at cycle n+m
. Cycle n is an arbitrary cycle.
before :: (AssertionValue dom a, AssertionValue dom b) => a -> b -> Assertion dom Source #
Same as a && next b
but with a nice syntax. E.g., a && next b
could
be written as a
. Might be read as "a happens one cycle before b".before
b
timplies :: (AssertionValue dom a, AssertionValue dom b) => a -> b -> Assertion dom Source #
timpliesOverlapping :: (AssertionValue dom a, AssertionValue dom b) => a -> b -> Assertion dom Source #
Same as implies
but strictly temporal.
always :: AssertionValue dom a => a -> Assertion dom Source #
Specify assertion should _always_ hold
never :: AssertionValue dom a => a -> Assertion dom Source #
Specify assertion should _never_ hold (not supported by SVA)
eventually :: AssertionValue dom a => a -> Assertion dom Source #
Specify assertion should _eventually_ hold
Asserts
assert :: AssertionValue dom a => a -> Property dom Source #
Check whether given assertion always holds. Results can be collected with
check
.
cover :: AssertionValue dom a => a -> Property dom Source #
Check whether given assertion holds for at least a single cycle. Results
can be collected with check
.
Assertion checking
:: (KnownDomain dom, HiddenClock dom, HiddenReset dom) | |
=> Text | Property name (used in reports and error messages) |
-> RenderAs | Assertion language to use in HDL |
-> Property dom | |
-> Signal dom AssertionResult |
:: (KnownDomain dom, HiddenClock dom, HiddenReset dom) | |
=> Text | Property name (used in reports and error messages) |
-> RenderAs | Assertion language to use in HDL |
-> Property dom | |
-> Signal dom a | |
-> Signal dom a |
Functions to deal with assertion results
hideAssertion :: Signal dom AssertionResult -> Signal dom a -> Signal dom a Source #
Print assertions in HDL