A synchronized signal with samples of type a, synchronized to clock clk, that has accumulated delay amount of samples delay along its path.

DSignal has the type role

>>> :i DSignal
type role DSignal nominal nominal representational
...

as it is safe to coerce the values in the signal, but not safe to coerce the synthesis domain or delay in the signal.

Delay a DSignal for d periods.

delay3
  :: KnownDomain dom
  => Clock dom
  -> Reset dom
  -> Enable dom
  -> DSignal dom n Int
  -> DSignal dom (n + 3) Int
delay3 clk rst en = delayed clk rst en (-1 :> -1 :> -1 :> Nil)

>>> sampleN 7 (delay3 systemClockGen resetGen enableGen (dfromList [0..]))
[-1,-1,-1,-1,1,2,3]

Delay a DSignal for d periods, where d is derived from the context.

delay2
  :: KnownDomain dom
  => Clock dom
  -> Reset dom
  -> Enable dom
  -> Int
  -> DSignal dom n Int
  -> DSignal dom (n + 2) Int
delay2 = delayedI

>>> sampleN 7 (delay2 systemClockGen resetGen enableGen (-1) (dfromList ([0..])))
[-1,-1,-1,1,2,3,4]

d can also be specified using type application:

>>> :t delayedI @3
delayedI @3
  :: ... =>
     Clock dom
     -> Reset dom
     -> Enable dom
     -> a
     -> DSignal dom n a
     -> DSignal dom (n + 3) a

Delay a DSignal for d cycles, the value at time 0..d-1 is a.

delayN2
  :: KnownDomain dom
  => Int
  -> Enable dom
  -> Clock dom
  -> DSignal dom n Int
  -> DSignal dom (n + 2) Int
delayN2 = delayN d2

>>> printX $ sampleN 6 (delayN2 (-1) enableGen systemClockGen (dfromList [1..]))
[-1,-1,1,2,3,4]

Delay a DSignal for d cycles, where d is derived from the context. The value at time 0..d-1 is a default value.

delayI2
  :: KnownDomain dom
  => Int
  -> Enable dom
  -> Clock dom
  -> DSignal dom n Int
  -> DSignal dom (n + 2) Int
delayI2 = delayI

>>> sampleN 6 (delayI2 (-1) enableGen systemClockGen (dfromList [1..]))
[-1,-1,1,2,3,4]

You can also use type application to do the same:

>>> sampleN 6 (delayI @2 (-1) enableGen systemClockGen (dfromList [1..]))
[-1,-1,1,2,3,4]

Tree fold over a Vec of DSignals with a combinatorial function, and delaying delay cycles after each application. Values at times 0..(delay*k)-1 are set to a default.

countingSignals :: Vec 4 (DSignal dom 0 Int)
countingSignals = repeat (dfromList [0..])

>>> printX $ sampleN 6 (delayedFold  d1 (-1) (+) enableGen systemClockGen countingSignals)
[-1,-2,0,4,8,12]

>>> printX $ sampleN 8 (delayedFold d2 (-1) (*) enableGen systemClockGen countingSignals)
[-1,-1,1,1,0,1,16,81]

Feed the delayed result of a function back to its input:

mac
  :: forall dom
   . KnownDomain dom
  => Clock dom
  -> Reset dom
  -> Enable dom
  -> DSignal dom 0 Int
  -> DSignal dom 0 Int
  -> DSignal dom 0 Int
mac clk rst en x y = feedback (mac' x y)
  where
    mac'
      :: DSignal dom 0 Int
      -> DSignal dom 0 Int
      -> DSignal dom 0 Int
      -> (DSignal dom 0 Int, DSignal dom 1 Int)
    mac' a b acc = let acc' = a * b + acc
                   in  (acc, delayedI clk rst en 0 acc')

>>> sampleN 7 (toSignal (mac systemClockGen systemResetGen enableGen (dfromList [0..]) (dfromList [0..])))
[0,0,1,5,14,30,55]

Signals are not delayed

Strip a DSignal of its delay information.

Create a DSignal from a list

Every element in the list will correspond to a value of the signal for one clock cycle.

>>> sampleN 2 (toSignal (dfromList [1,2,3,4,5]))
[1,2]

NB: This function is not synthesizable

Create a DSignal from a list

Every element in the list will correspond to a value of the signal for one clock cycle.

>>> sampleN 2 (toSignal (dfromList [1,2,3,4,5]))
[1,2]

NB: This function is not synthesizable

EXPERIMENTAL

Unsafely convert a Signal to a DSignal with an arbitrary delay.

NB: Should only be used to interface with functions specified in terms of Signal.

EXPERIMENTAL

Access a delayed signal from the future in the present. Often required When writing a circuit that requires feedback from itself.

mac
  :: KnownDomain dom
  => Clock dom
  -> Reset dom
  -> Enable dom
  -> DSignal dom 0 Int
  -> DSignal dom 0 Int
  -> DSignal dom 0 Int
mac clk rst en x y = acc'
  where
    acc' = (x * y) + antiDelay d1 acc
    acc  = delayedI clk rst en 0 acc'

EXPERIMENTAL

Access a delayed signal from the past in the present. In contrast with delayed and friends forward does not insert any logic. This means using this function violates the delay invariant of DSignal. This is sometimes useful when combining unrelated delayed signals where inserting logic is not wanted or when abstracting over internal delayed signals where the internal delay information should not be leaked.

For example, the circuit below returns a sequence of numbers as a pair but the internal delay information between the elements of the pair should not leak into the type.

numbers
  :: forall dom
   . KnownDomain dom
  => Clock dom
  -> Reset dom
  -> Enable dom
  -> DSignal dom 5 (Int, Int)
numbers clk rst en = DB.bundle (forward d1 s1, s2)
  where
    s1 :: DSignal dom 4 Int
    s1 = delayed clk rst en (100 :> 10 :> 5 :> 1 :> Nil) (pure 200)
    s2 :: DSignal dom 5 Int
    s2 = fmap (2*) $ delayN d1 0 en clk s1

>>> sampleN 8 (toSignal (numbers systemClockGen systemResetGen enableGen))
[(1,0),(1,2),(5,2),(10,10),(100,20),(200,200),(200,400),(200,400)]