{-|
Copyright  :  (C) 2017, Google Inc
                  2019, Myrtle Software Ltd
License    :  BSD2 (see the file LICENSE)
Maintainer :  Christiaan Baaij <christiaan.baaij@gmail.com>

DDR primitives for Intel FPGAs using ALTDDIO primitives.

For general information about DDR primitives see "Clash.Explicit.DDR".

Note that a reset is only available on certain devices,
see ALTDDIO userguide for the specifics:
<https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_altddio.pdf>
-}

{-# LANGUAGE CPP #-}
{-# LANGUAGE FlexibleContexts #-}
{-# LANGUAGE TypeFamilies #-}

module Clash.Intel.DDR
  ( altddioIn
  , altddioOut
  )
where

import GHC.Stack (HasCallStack, withFrozenCallStack)

import Clash.Annotations.Primitive (hasBlackBox)
import Clash.Explicit.Prelude
import Clash.Explicit.DDR

-- | Intel specific variant of 'ddrIn' implemented using the ALTDDIO_IN IP core.
--
-- Reset values are @0@
altddioIn
  :: ( HasCallStack
     , KnownConfiguration fast ('DomainConfiguration fast fPeriod edge reset init polarity)
     , KnownConfiguration slow ('DomainConfiguration slow (2*fPeriod) edge reset init polarity)
     , KnownNat m )
  => SSymbol deviceFamily
  -- ^ The FPGA family
  --
  -- For example this can be instantiated as follows:
  --
  -- > SSymbol @"Cyclone IV GX"
  -> Clock slow
  -- ^ clock
  -> Reset slow
  -- ^ reset
  -> Enable slow
  -- ^ Global enable
  -> Signal fast (BitVector m)
  -- ^ DDR input signal
  -> Signal slow (BitVector m,BitVector m)
  -- ^ normal speed output pairs
altddioIn :: SSymbol deviceFamily
-> Clock slow
-> Reset slow
-> Enable slow
-> Signal fast (BitVector m)
-> Signal slow (BitVector m, BitVector m)
altddioIn _devFam :: SSymbol deviceFamily
_devFam clk :: Clock slow
clk rst :: Reset slow
rst en :: Enable slow
en = (HasCallStack =>
 Clock slow
 -> Reset slow
 -> Enable slow
 -> BitVector m
 -> BitVector m
 -> BitVector m
 -> Signal fast (BitVector m)
 -> Signal slow (BitVector m, BitVector m))
-> Clock slow
-> Reset slow
-> Enable slow
-> BitVector m
-> BitVector m
-> BitVector m
-> Signal fast (BitVector m)
-> Signal slow (BitVector m, BitVector m)
forall a. HasCallStack => (HasCallStack => a) -> a
withFrozenCallStack HasCallStack =>
Clock slow
-> Reset slow
-> Enable slow
-> BitVector m
-> BitVector m
-> BitVector m
-> Signal fast (BitVector m)
-> Signal slow (BitVector m, BitVector m)
forall a (slow :: Domain) (fast :: Domain) (fPeriod :: Nat)
       (polarity :: ResetPolarity) (edge :: ActiveEdge)
       (reset :: ResetKind) (init :: InitBehavior).
(HasCallStack, NFDataX a,
 KnownConfiguration
   fast ('DomainConfiguration fast fPeriod edge reset init polarity),
 KnownConfiguration
   slow
   ('DomainConfiguration
      slow (2 * fPeriod) edge reset init polarity)) =>
Clock slow
-> Reset slow
-> Enable slow
-> a
-> a
-> a
-> Signal fast a
-> Signal slow (a, a)
ddrIn# Clock slow
clk Reset slow
rst Enable slow
en 0 0 0
{-# NOINLINE altddioIn #-}
{-# ANN altddioIn hasBlackBox #-}

-- | Intel specific variant of 'ddrOut' implemented using the ALTDDIO_OUT IP core.
--
-- Reset value is @0@
altddioOut
  :: ( HasCallStack
     , KnownConfiguration fast ('DomainConfiguration fast fPeriod edge reset init polarity)
     , KnownConfiguration slow ('DomainConfiguration slow (2*fPeriod) edge reset init polarity)
     , KnownNat m )
  => SSymbol deviceFamily
  -- ^ The FPGA family
  --
  -- For example this can be instantiated as follows:
  --
  -- > SSymbol @"Cyclone IV E"
  -> Clock slow
  -- ^ clock
  -> Reset slow
  -- ^ reset
  -> Enable slow
  -- ^ Global enable
  -> Signal slow (BitVector m,BitVector m)
  -- ^ normal speed input pair
  -> Signal fast (BitVector m)
  -- ^ DDR output signal
altddioOut :: SSymbol deviceFamily
-> Clock slow
-> Reset slow
-> Enable slow
-> Signal slow (BitVector m, BitVector m)
-> Signal fast (BitVector m)
altddioOut devFam :: SSymbol deviceFamily
devFam clk :: Clock slow
clk rst :: Reset slow
rst en :: Enable slow
en =
  (Signal slow (BitVector m)
 -> Signal slow (BitVector m) -> Signal fast (BitVector m))
-> (Signal slow (BitVector m), Signal slow (BitVector m))
-> Signal fast (BitVector m)
forall a b c. (a -> b -> c) -> (a, b) -> c
uncurry ((HasCallStack =>
 SSymbol deviceFamily
 -> Clock slow
 -> Reset slow
 -> Enable slow
 -> Signal slow (BitVector m)
 -> Signal slow (BitVector m)
 -> Signal fast (BitVector m))
-> SSymbol deviceFamily
-> Clock slow
-> Reset slow
-> Enable slow
-> Signal slow (BitVector m)
-> Signal slow (BitVector m)
-> Signal fast (BitVector m)
forall a. HasCallStack => (HasCallStack => a) -> a
withFrozenCallStack HasCallStack =>
SSymbol deviceFamily
-> Clock slow
-> Reset slow
-> Enable slow
-> Signal slow (BitVector m)
-> Signal slow (BitVector m)
-> Signal fast (BitVector m)
forall (fast :: Domain) (fPeriod :: Nat) (edge :: ActiveEdge)
       (reset :: ResetKind) (init :: InitBehavior)
       (polarity :: ResetPolarity) (slow :: Domain) (m :: Nat)
       (deviceFamily :: Domain).
(HasCallStack,
 KnownConfiguration
   fast ('DomainConfiguration fast fPeriod edge reset init polarity),
 KnownConfiguration
   slow
   ('DomainConfiguration slow (2 * fPeriod) edge reset init polarity),
 KnownNat m) =>
SSymbol deviceFamily
-> Clock slow
-> Reset slow
-> Enable slow
-> Signal slow (BitVector m)
-> Signal slow (BitVector m)
-> Signal fast (BitVector m)
altddioOut# SSymbol deviceFamily
devFam Clock slow
clk Reset slow
rst Enable slow
en) ((Signal slow (BitVector m), Signal slow (BitVector m))
 -> Signal fast (BitVector m))
-> (Signal slow (BitVector m, BitVector m)
    -> (Signal slow (BitVector m), Signal slow (BitVector m)))
-> Signal slow (BitVector m, BitVector m)
-> Signal fast (BitVector m)
forall b c a. (b -> c) -> (a -> b) -> a -> c
. Signal slow (BitVector m, BitVector m)
-> (Signal slow (BitVector m), Signal slow (BitVector m))
forall a (dom :: Domain).
Bundle a =>
Signal dom a -> Unbundled dom a
unbundle

altddioOut#
  :: ( HasCallStack
     , KnownConfiguration fast ('DomainConfiguration fast fPeriod edge reset init polarity)
     , KnownConfiguration slow ('DomainConfiguration slow (2*fPeriod) edge reset init polarity)
     , KnownNat m )
  => SSymbol deviceFamily
  -> Clock slow
  -> Reset slow
  -> Enable slow
  -> Signal slow (BitVector m)
  -> Signal slow (BitVector m)
  -> Signal fast (BitVector m)
altddioOut# :: SSymbol deviceFamily
-> Clock slow
-> Reset slow
-> Enable slow
-> Signal slow (BitVector m)
-> Signal slow (BitVector m)
-> Signal fast (BitVector m)
altddioOut# _ clk :: Clock slow
clk rst :: Reset slow
rst en :: Enable slow
en = Clock slow
-> Reset slow
-> Enable slow
-> BitVector m
-> Signal slow (BitVector m)
-> Signal slow (BitVector m)
-> Signal fast (BitVector m)
forall a (fast :: Domain) (fPeriod :: Nat) (edge :: ActiveEdge)
       (reset :: ResetKind) (init :: InitBehavior)
       (polarity :: ResetPolarity) (slow :: Domain).
(HasCallStack, NFDataX a,
 KnownConfiguration
   fast ('DomainConfiguration fast fPeriod edge reset init polarity),
 KnownConfiguration
   slow
   ('DomainConfiguration
      slow (2 * fPeriod) edge reset init polarity)) =>
Clock slow
-> Reset slow
-> Enable slow
-> a
-> Signal slow a
-> Signal slow a
-> Signal fast a
ddrOut# Clock slow
clk Reset slow
rst Enable slow
en 0
{-# NOINLINE altddioOut# #-}
{-# ANN altddioOut# hasBlackBox #-}