A synchronized signal with samples of type a, synchronized to clock clk, that has accumulated delay amount of samples delay along its path.

Delay a DSignal for d periods.

delay3
  :: KnownDomain dom
  => Clock dom
  -> Reset dom
  -> Enable dom
  -> DSignal dom n Int
  -> DSignal dom (n + 3) Int
delay3 clk rst en = delayed clk rst en (-1 :> -1 :> -1 :> Nil)

>>> sampleN 7 (delay3 systemClockGen resetGen enableGen (dfromList [0..]))
[-1,-1,-1,-1,1,2,3]

Delay a DSignal for d periods, where d is derived from the context.

delay2
  :: KnownDomain dom
  => Clock dom
  -> Reset dom
  -> Enable dom
  -> Int
  -> DSignal dom n Int
  -> DSignal dom (n + 2) Int
delay2 = delayedI

>>> sampleN 7 (delay2 systemClockGen resetGen enableGen (-1) (dfromList ([0..])))
[-1,-1,-1,1,2,3,4]

d can also be specified using type application:

>>> :t delayedI @3
delayedI @3
  :: ... =>
     Clock dom
     -> Reset dom
     -> Enable dom
     -> a
     -> DSignal dom n a
     -> DSignal dom (n + 3) a

Delay a DSignal for d cycles, the value at time 0..d-1 is a.

delayN2
  :: KnownDomain dom
  => Int
  -> Enable dom
  -> Clock dom
  -> DSignal dom n Int
  -> DSignal dom (n + 2) Int
delayN2 = delayN d2

>>> printX $ sampleN 6 (toSignal (delayN2 (-1) enableGen systemClockGen (dfromList [1..])))
[-1,-1,1,2,3,4]

Delay a DSignal for d cycles, where d is derived from the context. The value at time 0..d-1 is a default value.

delayI2
  :: KnownDomain dom
  => Int
  -> Enable dom
  -> Clock dom
  -> DSignal dom n Int
  -> DSignal dom (n + 2) Int
delayI2 = delayI

>>> sampleN 6 (toSignal (delayI2 (-1) enableGen systemClockGen (dfromList [1..])))
[-1,-1,1,2,3,4]

You can also use type application to do the same: >>> sampleN 6 (toSignal (delayI @2 (-1) enableGen systemClockGen (dfromList [1..]))) [-1,-1,1,2,3,4]

Tree fold over a Vec of DSignals with a combinatorial function, and delaying delay cycles after each application. Values at times 0..(delay*k)-1 are set to a default.

countingSignals :: Vec 4 (DSignal dom 0 Int)
countingSignals = repeat (dfromList [0..])

>>> printX $ sampleN 6 (toSignal (delayedFold  d1 (-1) (+) enableGen systemClockGen countingSignals))
[-1,-2,0,4,8,12]

>>> printX $ sampleN 8 (toSignal (delayedFold d2 (-1) (*) enableGen systemClockGen countingSignals))
[-1,-1,1,1,0,1,16,81]

Feed the delayed result of a function back to its input:

mac :: Clock dom -> Reset dom -> Enable dom
    -> DSignal dom 0 Int -> DSignal dom 0 Int -> DSignal dom 0 Int
mac clk rst en x y = feedback (mac' x y)
  where
    mac' :: DSignal dom 0 Int -> DSignal dom 0 Int -> DSignal dom 0 Int
         -> (DSignal dom 0 Int, DSignal dom 1 Int)
    mac' a b acc = let acc' = a * b + acc
                   in  (acc, delay clk rst en (singleton 0) acc')

>>> sampleN 7 (mac systemClockGen systemResetGen enableGen (dfromList [0..]) (dfromList [0..]))
[0,0,1,5,14,30,55]

Signals are not delayed

sample s == dsample (fromSignal s)

Strip a DSignal from its delay information.

Create a DSignal from a list

Every element in the list will correspond to a value of the signal for one clock cycle.

>>> sampleN 2 (dfromList [1,2,3,4,5])
[1,2]

NB: This function is not synthesizable

Create a DSignal from a list

Every element in the list will correspond to a value of the signal for one clock cycle.

>>> sampleN 2 (dfromList [1,2,3,4,5])
[1,2]

NB: This function is not synthesizable

EXPERIMENTAL

Unsafely convert a Signal to any DSignal clk'.

NB: Should only be used to interface with functions specified in terms of Signal.

EXPERIMENTAL

Access a delayed signal in the present.

mac :: Clock dom -> Reset dom -> Enable dom
    -> DSignal dom 0 Int -> DSignal dom 0 Int -> DSignal dom 0 Int
mac clk rst en x y = acc'
  where
    acc' = (x * y) + antiDelay d1 acc
    acc  = delay clk rst en (singleton 0) acc'